John; Jay P.

Patent Applications and Registrations

Patent applications and USPTO patent grants for John; Jay P..The latest application filed is for "methods for the fabrication of semiconductor devices including sub-isolation buried layers".

Company Profile

0.22.20

John; Jay P. - Chandler AZ US
John; Jay P - Chandler AZ

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor devices with recessed base electrode Grant 9,105,678 - John , et al. August 11, 2	2015-08-11
Electronic device including interconnects with a cavity therebetween and a process of forming the same Grant 9,099,445 - Trivedi , et al. August 4, 2	2015-08-04
Temperature sensor Grant 9,004,756 - John , et al. April 14, 2	2015-04-14
Methods For The Fabrication Of Semiconductor Devices Including Sub-isolation Buried Layers App 20140147985 - John; Jay P ; et al.	2014-05-29
Semiconductor Devices With Recessed Base Electrode App 20140131772 - JOHN; JAY P. ; et al.	2014-05-15
Bipolar transistor and method with recessed base electrode Grant 8,664,698 - John , et al. March 4, 2	2014-03-04
Electronic Device Including Interconnects With A Cavity Therebetween And A Process Of Forming The Same App 20140001650 - Trivedi; Vishal P. ; et al.	2014-01-02
Temperature Sensor App 20130266042 - John; Jay P. ; et al.	2013-10-10
Electronic device including interconnects with a cavity therebetween and a process of forming the same Grant 8,530,347 - Trivedi , et al. September 10, 2	2013-09-10
Double gate MOSFET with coplanar surfaces for contacting source, drain, and bottom gate Grant 8,530,972 - John , et al. September 10, 2	2013-09-10
Bipolar Transistor And Method With Recessed Base Electrode App 20120199881 - John; Jay P. ; et al.	2012-08-09
Electronic Device Including Interconnects With A Cavity Therebetween And A Process Of Forming The Same App 20120080804 - Trivedi; Vishal P. ; et al.	2012-04-05
Silicided base structure for high frequency transistors Grant 8,084,786 - John , et al. December 27, 2	2011-12-27
Method for Forming an Independent Bottom Gate Connection For Buried Interconnection Including Bottom Gate of a Planar Double Gate MOSFET App 20110215411 - John; Jay P. ; et al.	2011-09-08
Method of forming a bipolar transistor and semiconductor component thereof Grant 7,932,145 - John , et al. April 26, 2	2011-04-26
Silicided Base Structure For High Frequency Transistors App 20100314664 - John; Jay P. ; et al.	2010-12-16
Counter-doped varactor structure and method Grant 7,821,103 - Liu , et al. October 26, 2	2010-10-26
Dielectric ledge for high frequency devices Grant 7,816,221 - John , et al. October 19, 2	2010-10-19
Silicided base structure for high frequency transistors Grant 7,803,685 - John , et al. September 28, 2	2010-09-28
Method for forming an independent bottom gate connection for buried interconnection including bottom gate of a planar double gate MOSFET Grant 7,704,838 - John , et al. April 27, 2	2010-04-27
Counter-doped Varactor Structure And Method App 20100059860 - Liu; Chun-Li ; et al.	2010-03-11
Method Of Forming A Bipolar Transistor And Semiconductor Component Thereof App 20100013051 - John; Jay P. ; et al.	2010-01-21
Dielectric Ledge For High Frequency Devices App 20090321788 - John; Jay P. ; et al.	2009-12-31
Silicided Base Structure For High Frequency Transistors App 20090321879 - John; Jay P. ; et al.	2009-12-31
Integrated CMOS and bipolar devices method and structure Grant 7,638,386 - Kirchgessner , et al. December 29, 2	2009-12-29
Method of forming a bipolar transistor and semiconductor component thereof Grant 7,611,955 - John , et al. November 3, 2	2009-11-03
Method of manufacturing a bipolar transistor and bipolar transistor thereof Grant 7,442,616 - John , et al. October 28, 2	2008-10-28
Method of making planar double gate silicon-on-insulator structures Grant 7,341,915 - Li , et al. March 11, 2	2008-03-11
Method for forming an independent bottom gate connection for buried interconnection including bottom gate of a planar double gate MOSFET App 20080050902 - John; Jay P. ; et al.	2008-02-28
Method of manufacturing a bipolar transistor and bipolar transistor thereof App 20070290231 - John; Jay P. ; et al.	2007-12-20
Method of forming a bipolar transistor and semiconductor component thereof App 20070293013 - John; Jay P. ; et al.	2007-12-20
Integrated CMOS and bipolar devices method and structure App 20070293004 - Kirchgessner; James A. ; et al.	2007-12-20
Method of making planar double gate silicon-on-insulator structures App 20060270164 - Li; Philip ; et al.	2006-11-30

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