| Patent | Date |
|---|
Metal Cut Optimization For Standard Cells
App 20210271794 - Lei; Cheok-Kei ; et al. | 2021-09-02 |
System and Method for Transistor Placement in Standard Cell Layout
App 20210200927 - Lei; Cheok-Kei ; et al. | 2021-07-01 |
Capacitive Isolation Structure Insert For Reversed Signals
App 20210192118 - LEI; Cheok-Kei ; et al. | 2021-06-24 |
Metal cut optimization for standard cells
Grant 11,030,368 - Lei , et al. June 8, 2 | 2021-06-08 |
Layout Context-based Cell Timing Characterization
App 20210117603 - JIANG; ZHE-WEI ; et al. | 2021-04-22 |
Capacitive isolation structure insert for reversed signals
Grant 10,943,050 - Lei , et al. March 9, 2 | 2021-03-09 |
Metal Cut Optimization For Standard Cells
App 20200285792 - LEI; Cheok-Kei ; et al. | 2020-09-10 |
Layout For Integrated Circuit And The Integrated Circuit
App 20200285797 - LEI; CHEOK-KEI ; et al. | 2020-09-10 |
Metal cut optimization for standard cells
Grant 10,691,849 - Lei , et al. | 2020-06-23 |
Layout for integrated circuit and the integrated circuit
Grant 10,685,162 - Lei , et al. | 2020-06-16 |
Capacitive Isolation Structure Insert For Reversed Signals
App 20200134130 - LEI; Cheok-Kei ; et al. | 2020-04-30 |
Layout For Integrated Circuit And The Integrated Circuit
App 20190121931 - LEI; CHEOK-KEI ; et al. | 2019-04-25 |
Metal Cut Optimization for Standard Cells
App 20190095552 - LEI; Cheok-Kei ; et al. | 2019-03-28 |
Layout method for integrated circuit and layout of the integrated circuit
Grant 10,163,883 - Lei , et al. Dec | 2018-12-25 |
Layout Method For Integrated Circuit And Layout Of The Integrated Circuit
App 20170365592 - LEI; CHEOK-KEI ; et al. | 2017-12-21 |
Method and system of forming layout design
Grant 9,626,472 - Chiang , et al. April 18, 2 | 2017-04-18 |
Method and system of layout placement based on multilayer gridlines
Grant 9,536,032 - Chiang , et al. January 3, 2 | 2017-01-03 |
Method And System Of Forming Layout Design
App 20160147927 - CHIANG; Ting-Wei ; et al. | 2016-05-26 |
Method And System Of Forming Layout Design
App 20160147926 - CHIANG; Ting-Wei ; et al. | 2016-05-26 |
System and method for leakage estimation for standard integrated circuit cells with shared polycrystalline silicon-on-oxide definition-edge (PODE)
Grant 9,058,462 - Tam , et al. June 16, 2 | 2015-06-16 |
System And Method For Leakage Estimation For Standard Integrated Circuit Cells With Shared Polycrystalline Silicon-on-oxide Definition-edge (pode)
App 20150067624 - TAM; King-Ho ; et al. | 2015-03-05 |
Method of forming a layout including cells having different threshold voltages, a system of implementing and a layout formed
Grant 8,826,212 - Yeh , et al. September 2, 2 | 2014-09-02 |
Method Of Forming A Layout Including Cells Having Different Threshold Voltages, A System Of Implementing And A Layout Formed
App 20140165020 - YEH; Sung-Yen ; et al. | 2014-06-12 |
DFM improvement utility with unified interface
Grant 8,726,208 - Chen , et al. May 13, 2 | 2014-05-13 |
DFM Improvement Utility with Unified Interface
App 20130024832 - Chen; Wen-Hao ; et al. | 2013-01-24 |
Cell architecture and method
Grant 8,356,262 - Lu , et al. January 15, 2 | 2013-01-15 |
Cell Architecture And Method
App 20120331426 - LU; Lee-Chung ; et al. | 2012-12-27 |
Routing system and method for double patterning technology
Grant 8,239,806 - Chen , et al. August 7, 2 | 2012-08-07 |
Electrostatic Discharge Protection Scheme For Semiconductor Device Stacking Process
App 20110304010 - Jiang; Zhe-Wei ; et al. | 2011-12-15 |
Routing System And Method For Double Patterning Technology
App 20110119648 - Chen; Huang-Yu ; et al. | 2011-05-19 |
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