name:-0.018637895584106
name:-0.028966903686523
name:-0.0063810348510742
JIANG; XIAOHONG Patent Filings

JIANG; XIAOHONG

Patent Applications and Registrations

Patent applications and USPTO patent grants for JIANG; XIAOHONG.The latest application filed is for "chronic disease prediction system based on multi-task learning model".

Company Profile
4.23.13
  • JIANG; XIAOHONG - HANGZHOU ZHEJIANG PROVINCE
  • JIANG; XIAOHONG - Singapore SG
  • Jiang; Xiaohong - Shenzhen CN
  • JIANG; Xiaohong - San Jose CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Trademarks
Patent Activity
PatentDate
Chronic Disease Prediction System Based On Multi-task Learning Model
App 20220254493 - WU; JIAN ;   et al.
2022-08-11
Image sensor and manufacturing method thereof
App 20220165895 - Zhan; Zhaoyao ;   et al.
2022-05-26
Bike saddle
Grant D949,584 - Jiang April 26, 2
2022-04-26
Photosensitive Device
App 20210384231 - Zhan; Zhaoyao ;   et al.
2021-12-09
Bike saddle
Grant D930,375 - Jiang September 14, 2
2021-09-14
Gate-all-around (GAA) transistor and method of fabricating the same
Grant 11,101,361 - Zhan , et al. August 24, 2
2021-08-24
Method for stabilizing bandgap voltage
Grant 10,909,299 - Pang , et al. February 2, 2
2021-02-02
Chinese Medicine Production Process Knowledge System
App 20200350058 - XIAO; Wei ;   et al.
2020-11-05
Package Design Scheme For Enabling High-speed Low-loss Signaling And Mitigation Of Manufacturing Risk And Cost
App 20200343202 - WANG; Lijiang ;   et al.
2020-10-29
Magnetically decoupled inductor structures
Grant 9,941,201 - Jiang , et al. April 10, 2
2018-04-10
Tranmission line bridge interconnects
Grant 9,842,813 - Jiang , et al. December 12, 2
2017-12-12
Tranmission Line Bridge Interconnects
App 20170084553 - Jiang; Xiaohong ;   et al.
2017-03-23
Integrated circuit package routing with reduced crosstalk
Grant 9,425,149 - Jiang , et al. August 23, 2
2016-08-23
IC package with non-uniform dielectric layer thickness
Grant 9,401,330 - Jiang , et al. July 26, 2
2016-07-26
Multilayer integrated circuit packages with localized air structures
Grant 9,331,370 - Jiang May 3, 2
2016-05-03
Integrated circuit package with reduced pad capacitance
Grant 9,245,835 - Jiang , et al. January 26, 2
2016-01-26
High performance PCB
Grant 8,841,561 - Jiang , et al. September 23, 2
2014-09-23
Apparatus For Electronic Assembly With Improved Interconnect And Associated Methods
App 20140264783 - Liu; Hui ;   et al.
2014-09-18
Compensation network using an on-die compensation inductor
Grant 8,723,293 - Jiang , et al. May 13, 2
2014-05-13
Vertically tapered transmission line for optimal signal transition in high-speed multi-layer ball grid array packages
Grant 8,502,386 - Jiang , et al. August 6, 2
2013-08-06
Compensation network using an on-die compensation inductor
Grant 8,368,174 - Jiang , et al. February 5, 2
2013-02-05
Interconnect pattern for transceiver package
Grant 8,294,259 - Jiang , et al. October 23, 2
2012-10-23
Interconnect Pattern For Transceiver Package
App 20110193233 - Jiang; Xiaohong ;   et al.
2011-08-11
Vertically tapered transmission line for optimal signal transition in high-speed multi-layer ball grid array packages
Grant 7,752,587 - Jiang , et al. July 6, 2
2010-07-06
Vertically Tapered Transmission Line for Optimal Signal Transition in High-Speed Multi-Layer Ball Grid Array Packages
App 20100148375 - Jiang; Xiaohong ;   et al.
2010-06-17
Semiconductor device layout and channeling implant process
Grant 7,573,099 - Li , et al. August 11, 2
2009-08-11
Vertically Tapered Transmission Line For Optimal Signal Transition In High-speed Multi-layer Ball Grid Array Packages
App 20090077523 - Jiang; Xiaohong ;   et al.
2009-03-19
Semiconductor device layout and channeling implant process
Grant 7,253,483 - Li , et al. August 7, 2
2007-08-07
Semiconductor device layout and channeling implant process
App 20050280082 - Li, Yisuo ;   et al.
2005-12-22
Semiconductor device layout and channeling implant process
Grant 6,972,236 - Li , et al. December 6, 2
2005-12-06
Semiconductor device layout and channeling implant process
App 20050236677 - Li, Yisuo ;   et al.
2005-10-27
Semiconductor Device Layout And Channeling Implant Process
App 20050170595 - Li, Yisuo ;   et al.
2005-08-04

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed