Jha; Ashish Kumar

Patent Applications and Registrations

Patent applications and USPTO patent grants for Jha; Ashish Kumar.The latest application filed is for "rapid content deployment on a publication platform".

Company Profile

8.12.9

Jha; Ashish Kumar - Pune IN
Jha; Ashish Kumar - Hadapsar Pune IN
Jha; Ashish Kumar - Ballston Lake NY
Jha; Ashish Kumar - Saratoga Springs NY
Jha; Ashish Kumar - Pleasanton CA
JHA; Ashish Kumar - Noida IN
Jha; Ashish Kumar - Clifton Park NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Rapid content deployment on a publication platform Grant 11,170,117 - Jha November 9, 2	2021-11-09
Optimizing allocation of configuration elements Grant 10,521,811 - Rai , et al. Dec	2019-12-31
Selective shallow trench isolation (STI) fill for stress engineering in semiconductor structures Grant 10,522,679 - Jha , et al. Dec	2019-12-31
Rapid Content Deployment On A Publication Platform App 20190377888 - Jha; Ashish Kumar	2019-12-12
Gate cut method Grant 10,396,206 - Jha , et al. A	2019-08-27
Selective Shallow Trench Isolation (sti) Fill For Stress Engineering In Semiconductor Structures App 20190131452 - JHA; Ashish Kumar ; et al.	2019-05-02
Sti Inner Spacer To Mitigate Sdb Loading App 20190035633 - Jha; Ashish Kumar ; et al.	2019-01-31
STI inner spacer to mitigate SDB loading Grant 10,192,746 - Jha , et al. Ja	2019-01-29
Gate Cut Method App 20190013245 - JHA; Ashish Kumar ; et al.	2019-01-10
Enlarged sacrificial gate caps for forming self-aligned contacts Grant 10,008,385 - Jha , et al. June 26, 2	2018-06-26
Low-VOC cleaning substrates and compositions containing a non-ionic surfactant Grant 9,988,594 - Hope , et al. June 5, 2	2018-06-05
System and method for multi-layered monitoring and control for dynamic situation handling for production support Grant 9,946,987 - Rai , et al. April 17, 2	2018-04-17
Methods to thin down RMG sidewall layers for scalability of gate-last planar CMOS and FinFET technology Grant 9,443,771 - Shen , et al. September 13, 2	2016-09-13
Fabricating transistor(s) with raised active regions having angled upper surfaces Grant 9,331,159 - Jha , et al. May 3, 2	2016-05-03
System And Method For Data Transfer Among The Devices App 20150339261 - JHA; Ashish Kumar ; et al.	2015-11-26
Using sacrificial oxide layer for gate length tuning and resulting device Grant 9,147,572 - Jha , et al. September 29, 2	2015-09-29
Optimizing Allocation of Configuration Elements App 20150106143 - Rai; Veerendra Kumar ; et al.	2015-04-16
Obtaining Optimal Pricing Strategy In A Service Engagement App 20150106163 - RAI; Veerendra Kumar ; et al.	2015-04-16
System and Method for Multi-Layered Monitoring and Control for Dynamic Situation Handling for Production Support App 20150106165 - Rai; Veerendra Kumar ; et al.	2015-04-16
Low-VOC cleaning substrates and compositions comprising a cationic biocide and glycol ether solvent Grant 9,006,165 - Mitchell , et al. April 14, 2	2015-04-14
Using Sacrificial Oxide Layer For Gate Length Tuning And Resulting Device App 20140339612 - JHA; Ashish Kumar ; et al.	2014-11-20

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