loadpatents
name:-0.011738061904907
name:-0.0068728923797607
name:-0.00045895576477051
Jessen; Scott Patent Filings

Jessen; Scott

Patent Applications and Registrations

Patent applications and USPTO patent grants for Jessen; Scott.The latest application filed is for "mask layer and interconnect structure for dual damascene semiconductor manufacturing".

Company Profile
0.7.8
  • Jessen; Scott - Orlando FL
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Mask layer and dual damascene interconnect structure in a semiconductor device
Grant 7,067,419 - Huang , et al. June 27, 2
2006-06-27
Substrate topography compensation at mask design: 3D OPC topography anchored
Grant 6,893,800 - Jessen , et al. May 17, 2
2005-05-17
Split barrier layer including nitrogen-containing portion and oxygen-containing portion
Grant 6,879,046 - Gibson, Jr. , et al. April 12, 2
2005-04-12
Structure and method for isolating porous low-k dielectric films
Grant 6,798,043 - Steiner , et al. September 28, 2
2004-09-28
Mask layer and interconnect structure for dual damascene semiconductor manufacturing
App 20040171256 - Oladeji, Isaiah O. ;   et al.
2004-09-02
Mask layer and dual damascene interconnect structure in a semiconductor device
App 20040121579 - Huang, Robert YS ;   et al.
2004-06-24
Substrate topography compensation at mask design: 3D OPC topography anchored
App 20040058255 - Jessen, Scott ;   et al.
2004-03-25
Abnormal photoresist line/space profile detection through signal processing of metrology waveform
Grant 6,708,574 - Houge , et al. March 23, 2
2004-03-23
Bond pad support structure for a semiconductor device
App 20030218259 - Chesire, Daniel Patrick ;   et al.
2003-11-27
Method of focused ion beam pattern transfer using a smart dynamic template
Grant 6,627,885 - McIntosh , et al. September 30, 2
2003-09-30
Mask layer and dual damascene interconnect structure in a semiconductor device
App 20030119305 - Huang, Robert Y. S. ;   et al.
2003-06-26
Mask layer and interconnect structure for dual damascene semiconductor manufacturing
App 20030064582 - Oladeji, Isaiah O. ;   et al.
2003-04-03
Structure and method for isolating porous low-k dielectric films
App 20030001273 - Steiner, Kurt G. ;   et al.
2003-01-02
Split barrier layer including nitrogen-containing portion and oxygen-containing portion
App 20030003765 - Gibson, Gerald W. JR. ;   et al.
2003-01-02
Method analyzing a semiconductor surface using line width metrology with auto-correlation operation
Grant 6,258,610 - Blatchford , et al. July 10, 2
2001-07-10

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed