JEONG; Kwang Ok

Patent Applications and Registrations

Patent applications and USPTO patent grants for JEONG; Kwang Ok.The latest application filed is for "fan-out semiconductor package".

Company Profile

7.7.15

JEONG; Kwang Ok - Suwon-si KR
Jeong; Kwang-ok - Hwaseong-si KR
Jeong; Kwang Ok - Gyeonggi-do KR
Jeong; Kwang-Ok - Gwangmyeong-si KR
Jeong; Kwang-ok - Seoul KR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Fan-out Semiconductor Package App 20210151370 - CHOI; Ik Jun ; et al.	2021-05-20
Fan-out semiconductor package Grant 10,916,495 - Choi , et al. February 9, 2	2021-02-09
System and method of designing integrated circuit by considering local layout effect Grant 10,817,637 - Ha , et al. October 27, 2	2020-10-27
Semiconductor package Grant 10,811,352 - Jeong October 20, 2	2020-10-20
Semiconductor Package App 20200105665 - Jeong; Kwang Ok	2020-04-02
Semiconductor package Grant 10,446,478 - Jeong , et al. Oc	2019-10-15
Integrated circuit for reducing ohmic drop in power rails Grant 10,340,263 - Won , et al.	2019-07-02
Fan-out Semiconductor Package App 20190131224 - Choi; Ik Jun ; et al.	2019-05-02
Semiconductor Package App 20190131225 - JEONG; Kwang Ok ; et al.	2019-05-02
Integrated Circuit For Reducing Ohmic Drop In Power Rails App 20180166432 - WON; HYO SIG ; et al.	2018-06-14
System And Method Of Designing Integrated Circuit By Considering Local Layout Effect App 20180032658 - HA; Naya ; et al.	2018-02-01
Computer-implemented Method Of Designing An Integrated Circuit App 20170344692 - OH; SUNG-MIN ; et al.	2017-11-30
Method Of Analyzing Semiconductor Devices And Analysis Apparatus For Semiconductor Devices App 20170262557 - SHIMAZU; KATSUHIRO ; et al.	2017-09-14
Double patterning layout design method Grant 9,098,670 - Song , et al. August 4, 2	2015-08-04
Double Patterning Layout Design Method App 20140380256 - SONG; TAE-JOONG ; et al.	2014-12-25
Via Hole Plating Method And Printed Circuit Board Manufactured Using The Same App 20130140074 - Yang; Jae Joon ; et al.	2013-06-06
Plating method of substrate and manufacturing method of circuit board using the same App 20120123574 - Moon; Jeong-Ho ; et al.	2012-05-17
Method for forming a plating layer and method for manufacturing a circuit board using the same App 20120031550 - Moon; Jeong-Ho ; et al.	2012-02-09
Method for manufacturing package on package with cavity App 20100006446 - Kim; Chi-Seong ; et al.	2010-01-14
Printed circuit board having inner via hole and manufacturing method thereof App 20070199735 - Kim; Chi-Seong ; et al.	2007-08-30
Clocked-scan flip-flop for multi-threshold voltage CMOS circuit Grant 6,861,887 - Jeong , et al. March 1, 2	2005-03-01
Clocked-scan flip-flop for multi-threshold voltage CMOS circuit App 20040021493 - Jeong, Kwang-ok ; et al.	2004-02-05

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