Jeng; Shwu-Jen

Patent Applications and Registrations

Patent applications and USPTO patent grants for Jeng; Shwu-Jen.The latest application filed is for "method of forming source and drain of a field-effect-transistor and structure thereof".

Company Profile

0.16.15

Jeng; Shwu-Jen - Wappingers Falls NY US
Jeng; Shwu-Jen - Wappingers Fall NY
Jeng; Shwu-Jen - Fishkill NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor structure having undercut-gate-oxide gate stack enclosed by protective barrier material Grant 8,754,446 - Chen , et al. June 17, 2	2014-06-17
Method of forming source and drain of a field-effect-transistor and structure thereof Grant 8,084,788 - Holt , et al. December 27, 2	2011-12-27
Method Of Forming Source And Drain Of A Field-effect-transistor And Structure Thereof App 20100090288 - Holt; Judson R. ; et al.	2010-04-15
Transistor structure with minimized parasitics and method of fabricating the same Grant 7,642,569 - Greenberg , et al. January 5, 2	2010-01-05
Transistor Structure With Minimized Parasitics And Method Of Fabricating The Same App 20090134429 - Greenberg; David R. ; et al.	2009-05-28
Transistor structure with minimized parasitics and method of fabricating the same Grant 7,491,617 - Greenberg , et al. February 17, 2	2009-02-17
Method of making a semiconductor structure Grant 7,491,623 - Chen , et al. February 17, 2	2009-02-17
Semiconductor Structure And Method Of Making Same App 20080121931 - Chen; Xiaomeng ; et al.	2008-05-29
Semiconductor Structure And Method Of Making Same App 20080057673 - CHEN; Xiaomeng ; et al.	2008-03-06
Transistor Structure With Minimized Parasitics And Method Of Fabricating The Same App 20070241428 - Greenberg; David R. ; et al.	2007-10-18
Transistor structure with minimized parasitics and method of fabricating the same Grant 7,253,070 - Greenberg , et al. August 7, 2	2007-08-07
Transistor structure with minimized parasitics and method of fabricating the same App 20060249814 - Greenberg; David R. ; et al.	2006-11-09
Transistor structure with minimized parasitics and method of fabricating the same Grant 7,075,126 - Greenberg , et al. July 11, 2	2006-07-11
Method of fabrication of MIMCAP and resistor at same level Grant 7,022,246 - Chinthakindi , et al. April 4, 2	2006-04-04
Transistor structure with minimized parasitics and method of fabricating the same App 20050191911 - Greenberg, David R. ; et al.	2005-09-01
Bipolar device having shallow junction raised extrinsic base and method for making the same Grant 6,927,476 - Freeman , et al. August 9, 2	2005-08-09
Structure and method for formation of a bipolar resistor App 20050095787 - Ballantine, Arne W. ; et al.	2005-05-05
Method to fabricate SiGe HBTs with controlled current gain and improved breakdown voltage characteristics Grant 6,787,427 - Greenberg , et al. September 7, 2	2004-09-07
Method of fabrication of MIMCAP and resistor at same level App 20040130434 - Chinthakindi, Anil K. ; et al.	2004-07-08
Method to fabricate SiGe HBTs with controlled current gain and improved breakdown voltage characteristics App 20040063293 - Greenberg, David R. ; et al.	2004-04-01
Structure and method for formation of a blocked silicide resistor Grant 6,660,664 - Adkisson , et al. December 9, 2	2003-12-09
Method to fabricate SiGe HBTs with controlled current gain and improved breakdown voltage characteristics Grant 6,656,809 - Greenberg , et al. December 2, 2	2003-12-02
Method to fabricate SiGe HBTs with controlled current gain and improved breakdown voltage characteristics App 20030132453 - Greenberg, David R. ; et al.	2003-07-17
Bipolar device having shallow junction raised extrinsic base and method for making the same App 20030057458 - Freeman, Gregory G. ; et al.	2003-03-27
Dual sidewall spacer for a self-aligned extrinsic base in SiGe heterojunction bipolar transistors Grant 6,531,720 - Freeman , et al. March 11, 2	2003-03-11
Non-self-aligned SiGe heterojunction bipolar transistor App 20020197807 - Jagannathan, Basanth ; et al.	2002-12-26
Dual sidewall spacer for a self-aligned extrinsic base in SiGe heterojunction bipolar transistors App 20020153535 - Freeman, Gregory G. ; et al.	2002-10-24
Stepped collector implant and method for fabrication App 20020132434 - Freeman, Gregory G. ; et al.	2002-09-19
Supersonic molecular beam etching of surfaces Grant 5,286,331 - Chen , et al. February 15, 1	1994-02-15
Device and method for accurate etching and removal of thin film Grant 5,282,925 - Jeng , et al. February 1, 1	1994-02-01

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.