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Patent applications and USPTO patent grants for Jeng; Chih-Cherng.The latest application filed is for "cis image sensors with epitaxy layers and methods for forming the same".
Patent | Date |
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Method for increasing photodiode full well capacity Grant 8,951,826 - Jeng , et al. February 10, 2 | 2015-02-10 |
CIS image sensors with epitaxy layers and methods for forming the same Grant 8,889,461 - JangJian , et al. November 18, 2 | 2014-11-18 |
Dual profile shallow trench isolation apparatus and system Grant 8,872,301 - Hung , et al. October 28, 2 | 2014-10-28 |
Image sensor cross-talk reduction system Grant 8,860,101 - Chang , et al. October 14, 2 | 2014-10-14 |
Structures for grounding metal shields in backside illumination image sensor chips Grant 8,803,271 - Liu , et al. August 12, 2 | 2014-08-12 |
Implanting method for forming photodiode Grant 8,652,868 - Shih , et al. February 18, 2 | 2014-02-18 |
Annealing methods for backside illumination image sensor chips Grant 8,628,998 - Lin , et al. January 14, 2 | 2014-01-14 |
CIS Image Sensors with Epitaxy Layers and Methods for Forming the Same App 20130320419 - JangJian; Shiu-Ko ;   et al. | 2013-12-05 |
Dual Profile Shallow Trench Isolation Apparatus and System App 20130277790 - Hung; Chia-Yang ;   et al. | 2013-10-24 |
Implanting Method for Forming Photodiode App 20130230941 - Shih; Yu-Shen ;   et al. | 2013-09-05 |
Image Sensor Cross-Talk Reduction System and Method App 20130207220 - Chang; Lan Fang ;   et al. | 2013-08-15 |
Method for Increasing Photodiode Full Well Capacity App 20130193539 - Jeng; Jung-Chi ;   et al. | 2013-08-01 |
Annealing Methods for Backside Illumination Image Sensor Chips App 20130171766 - Lin; Yu-Ting ;   et al. | 2013-07-04 |
Feature dimension measurement Grant 8,049,213 - Su , et al. November 1, 2 | 2011-11-01 |
Seal ring structure for integrated circuit chips Grant 7,777,338 - Yao , et al. August 17, 2 | 2010-08-17 |
Feature Dimension Measurement App 20090152545 - Su; Ching-Chung ;   et al. | 2009-06-18 |
Seal ring structure for integrated circuit chips App 20060055007 - Yao; Chih-Hsiang ;   et al. | 2006-03-16 |
Methods for enhancing die saw and packaging reliability App 20060055002 - Yao; Chih-Hsiang ;   et al. | 2006-03-16 |
Vertical nanotube transistor and process for fabricating the same App 20040004235 - Lee, Chun-Tao ;   et al. | 2004-01-08 |
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