Jen; Wei-Lun K.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Jen; Wei-Lun K..The latest application filed is for "novel lga architecture for improving reliability performance of metal defined pads".

Company Profile

6.6.11

Jen; Wei-Lun K. - Chandler AZ

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Methods of forming a package substrate Grant 11,443,970 - Konchady , et al. September 13, 2	2022-09-13
Novel Lga Architecture For Improving Reliability Performance Of Metal Defined Pads App 20220199503 - DUBEY; Manish ; et al.	2022-06-23
Package With Underfill Containment Barrier App 20210391232 - Jain; Rahul ; et al.	2021-12-16
Package with underfill containment barrier Grant 11,158,558 - Jain , et al. October 26, 2	2021-10-26
Package With Underfill Containment Barrier App 20210111088 - Jain; Rahul ; et al.	2021-04-15
Sacrificial Pads To Prevent Galvanic Corrosion Of Fli Bumps In Emib Packages App 20210035818 - IBRAHIM; Tarek A. ; et al.	2021-02-04
Substrate Patch Reconstitution Options App 20200294920 - HARIRI; Haifa ; et al.	2020-09-17
Methods To Pattern Tfc And Incorporation In The Odi Architecture And In Any Build Up Layer Of Organic Substrate App 20200294938 - JAIN; Rahul ; et al.	2020-09-17
Solder Resist Layers For Coreless Packages And Methods Of Fabrication App 20200194300 - KONCHADY; Manohar S. ; et al.	2020-06-18
Solder resist layers for coreless packages and methods of fabrication Grant 10,629,469 - Konchady , et al.	2020-04-21
High resolution solder resist material for silicon bridge application Grant 10,020,262 - Alur , et al. July 10, 2	2018-07-10
High Resolution Solder Resist Material For Silicon Bridge Application App 20180005946 - ALUR; SIDDHARTH K. ; et al.	2018-01-04
Dual Side Solder Resist Layers For Coreless Packages And Packages With An Embedded Interconnect Bridge And Their Methods Of Fabrication App 20170250150 - KONCHADY; Manohar S. ; et al.	2017-08-31
Dual side solder resist layers for coreless packages and packages with an embedded interconnect bridge and their methods of fabrication Grant 9,704,735 - Konchady , et al. July 11, 2	2017-07-11
Dual Side Solder Resist Layers For Coreless Packages And Packages With An Embedded Interconnect Bridge And Their Methods Of Fabrication App 20160056102 - Konchady; Manohar S. ; et al.	2016-02-25

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.