loadpatents
name:-0.013800859451294
name:-0.016664981842041
name:-0.0049121379852295
Jeganathan; Dhivya Patent Filings

Jeganathan; Dhivya

Patent Applications and Registrations

Patent applications and USPTO patent grants for Jeganathan; Dhivya.The latest application filed is for "processor providing intelligent management of values buffered in overlaid architected and non-architected register files".

Company Profile
6.18.18
  • Jeganathan; Dhivya - Austin TX
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Processor providing intelligent management of values buffered in overlaid architected and non-architected register files
Grant 11,327,757 - Battle , et al. May 10, 2
2022-05-10
Processor Providing Intelligent Management Of Values Buffered In Overlaid Architected And Non-architected Register Files
App 20210342150 - Battle; Steven J. ;   et al.
2021-11-04
Finish Exception Handling Of An Instruction Completion Table
App 20210271487 - Ward; Kenneth L. ;   et al.
2021-09-02
Finish exception handling of an instruction completion table
Grant 11,086,630 - Ward , et al. August 10, 2
2021-08-10
Merging status and control data in a reservation station
Grant 10,719,056 - Barrick , et al.
2020-07-21
Variable latency pipe for interleaving instruction tags in a microprocessor
Grant 10,649,779 - Ayub , et al.
2020-05-12
Variable latency pipe for interleaving instruction tags in a microprocessor
Grant 10,613,868 - Ayub , et al.
2020-04-07
On-demand GPR ECC error detection and scrubbing for a multi-slice microprocessor
Grant 10,489,253 - Battle , et al. Nov
2019-11-26
Broadcasting messages between execution slices for issued instructions indicating when execution results are ready
Grant 10,445,100 - Ayub , et al. Oc
2019-10-15
Partial ECC mechanism for a byte-write capable register
Grant 10,176,038 - Jeganathan , et al. J
2019-01-08
On-demand Gpr Ecc Error Detection And Scrubbing For A Multi-slice Microprocessor
App 20180336108 - BATTLE; Steven J. ;   et al.
2018-11-22
Operation of a multi-slice processor implementing a mechanism to overcome a system hang
Grant 10,031,757 - Brownscheidle , et al. July 24, 2
2018-07-24
Generating ECC values for byte-write capable registers
Grant 9,985,655 - Jeganathan , et al. May 29, 2
2018-05-29
Operation of a multi-slice processor implementing dynamic switching of instruction issuance order
Grant 9,983,879 - Brownscheidle , et al. May 29, 2
2018-05-29
Generating ECC values for byte-write capable registers
Grant 9,985,656 - Jeganathan , et al. May 29, 2
2018-05-29
Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor
Grant 9,959,123 - Bowman , et al. May 1, 2
2018-05-01
Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor
Grant 9,928,073 - Bowman , et al. March 27, 2
2018-03-27
Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor
Grant 9,921,833 - Bowman , et al. March 20, 2
2018-03-20
Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor
Grant 9,858,078 - Bowman , et al. January 2, 2
2018-01-02
Transmitting Data Between Execution Slices Of A Multi-slice Processor
App 20170357513 - AYUB; SALMA ;   et al.
2017-12-14
Merging Status And Control Data In A Reservation Station
App 20170315528 - Barrick; Brian ;   et al.
2017-11-02
Partial ECC handling for a byte-write capable register
Grant 9,766,975 - Jeganathan , et al. September 19, 2
2017-09-19
Operation Of A Multi-slice Processor Implementing Dynamic Switching Of Instruction Issuance Order
App 20170255463 - BROWNSCHEIDLE; JEFFREY C. ;   et al.
2017-09-07
Operation Of A Multi-slice Processor Implementing A Mechanism To Overcome A System Hang
App 20170235577 - BROWNSCHEIDLE; JEFFREY C. ;   et al.
2017-08-17
Operation Of A Multi-slice Processor With Speculative Data Loading
App 20170168821 - BOWMAN; JOSHUA W. ;   et al.
2017-06-15
Operation Of A Multi-slice Processor With Speculative Data Loading
App 20170168836 - BOWMAN; JOSHUA W. ;   et al.
2017-06-15
Parity protection of a register
Grant 9,639,418 - Bowman , et al. May 2, 2
2017-05-02
Partial Ecc Mechanism For A Byte-write Capable Register
App 20170063401 - JEGANATHAN; Dhivya ;   et al.
2017-03-02
Generating Ecc Values For Byte-write Capable Registers
App 20170060677 - JEGANATHAN; Dhivya ;   et al.
2017-03-02
Generating Ecc Values For Byte-write Capable Registers
App 20170060679 - JEGANATHAN; Dhivya ;   et al.
2017-03-02
Partial Ecc Handling For A Byte-write Capable Register
App 20170060678 - JEGANATHAN; Dhivya ;   et al.
2017-03-02
Parity Protection Of A Register
App 20170060673 - Bowman; Joshua W. ;   et al.
2017-03-02
Variable Latency Pipe For Interleaving Instruction Tags In A Microprocessor
App 20170003971 - Ayub; Salma ;   et al.
2017-01-05
Variable Latency Pipe For Interleaving Instruction Tags In A Microprocessor
App 20170003969 - AYUB; Salma ;   et al.
2017-01-05
Speculative Load Data in Byte-Write Capable Register File and History Buffer for a Multi-Slice Microprocessor
App 20160357566 - Bowman; Joshua W. ;   et al.
2016-12-08
Speculative Load Data in Byte-Write Capable Register File and History Buffer for a Multi-Slice Microprocessor
App 20160357567 - Bowman; Joshua W. ;   et al.
2016-12-08

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