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Variable latency pipe for interleaving instruction tags in a microprocessor Grant 10,649,779 - Ayub , et al. | 2020-05-12 |
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On-demand GPR ECC error detection and scrubbing for a multi-slice microprocessor Grant 10,489,253 - Battle , et al. Nov | 2019-11-26 |
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Partial ECC mechanism for a byte-write capable register Grant 10,176,038 - Jeganathan , et al. J | 2019-01-08 |
On-demand Gpr Ecc Error Detection And Scrubbing For A Multi-slice Microprocessor App 20180336108 - BATTLE; Steven J. ;   et al. | 2018-11-22 |
Operation of a multi-slice processor implementing a mechanism to overcome a system hang Grant 10,031,757 - Brownscheidle , et al. July 24, 2 | 2018-07-24 |
Generating ECC values for byte-write capable registers Grant 9,985,655 - Jeganathan , et al. May 29, 2 | 2018-05-29 |
Operation of a multi-slice processor implementing dynamic switching of instruction issuance order Grant 9,983,879 - Brownscheidle , et al. May 29, 2 | 2018-05-29 |
Generating ECC values for byte-write capable registers Grant 9,985,656 - Jeganathan , et al. May 29, 2 | 2018-05-29 |
Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor Grant 9,959,123 - Bowman , et al. May 1, 2 | 2018-05-01 |
Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor Grant 9,928,073 - Bowman , et al. March 27, 2 | 2018-03-27 |
Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor Grant 9,921,833 - Bowman , et al. March 20, 2 | 2018-03-20 |
Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor Grant 9,858,078 - Bowman , et al. January 2, 2 | 2018-01-02 |
Transmitting Data Between Execution Slices Of A Multi-slice Processor App 20170357513 - AYUB; SALMA ;   et al. | 2017-12-14 |
Merging Status And Control Data In A Reservation Station App 20170315528 - Barrick; Brian ;   et al. | 2017-11-02 |
Partial ECC handling for a byte-write capable register Grant 9,766,975 - Jeganathan , et al. September 19, 2 | 2017-09-19 |
Operation Of A Multi-slice Processor Implementing Dynamic Switching Of Instruction Issuance Order App 20170255463 - BROWNSCHEIDLE; JEFFREY C. ;   et al. | 2017-09-07 |
Operation Of A Multi-slice Processor Implementing A Mechanism To Overcome A System Hang App 20170235577 - BROWNSCHEIDLE; JEFFREY C. ;   et al. | 2017-08-17 |
Operation Of A Multi-slice Processor With Speculative Data Loading App 20170168821 - BOWMAN; JOSHUA W. ;   et al. | 2017-06-15 |
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Parity protection of a register Grant 9,639,418 - Bowman , et al. May 2, 2 | 2017-05-02 |
Partial Ecc Mechanism For A Byte-write Capable Register App 20170063401 - JEGANATHAN; Dhivya ;   et al. | 2017-03-02 |
Generating Ecc Values For Byte-write Capable Registers App 20170060677 - JEGANATHAN; Dhivya ;   et al. | 2017-03-02 |
Generating Ecc Values For Byte-write Capable Registers App 20170060679 - JEGANATHAN; Dhivya ;   et al. | 2017-03-02 |
Partial Ecc Handling For A Byte-write Capable Register App 20170060678 - JEGANATHAN; Dhivya ;   et al. | 2017-03-02 |
Parity Protection Of A Register App 20170060673 - Bowman; Joshua W. ;   et al. | 2017-03-02 |
Variable Latency Pipe For Interleaving Instruction Tags In A Microprocessor App 20170003971 - Ayub; Salma ;   et al. | 2017-01-05 |
Variable Latency Pipe For Interleaving Instruction Tags In A Microprocessor App 20170003969 - AYUB; Salma ;   et al. | 2017-01-05 |
Speculative Load Data in Byte-Write Capable Register File and History Buffer for a Multi-Slice Microprocessor App 20160357566 - Bowman; Joshua W. ;   et al. | 2016-12-08 |
Speculative Load Data in Byte-Write Capable Register File and History Buffer for a Multi-Slice Microprocessor App 20160357567 - Bowman; Joshua W. ;   et al. | 2016-12-08 |