loadpatents
Patent applications and USPTO patent grants for Jaynes; Paul.The latest application filed is for "electronic and optoelectronic component packaging technique".
Patent | Date |
---|---|
Chip package sealing method Grant 7,972,901 - Farrell , et al. July 5, 2 | 2011-07-05 |
Electronic and optoelectronic component packaging technique Grant 7,476,566 - Farrell , et al. January 13, 2 | 2009-01-13 |
Chip package sealing method Grant 6,977,187 - Farrell , et al. December 20, 2 | 2005-12-20 |
Electronic and optoelectronic component packaging technique App 20050260797 - Farrell, Brian ;   et al. | 2005-11-24 |
Electronic and optoelectronic component packaging technique Grant 6,952,046 - Farrell , et al. October 4, 2 | 2005-10-04 |
Chip package sealing method App 20050189332 - Farrell, Brian ;   et al. | 2005-09-01 |
Chip package sealing method App 20040010910 - Farrell, Brian ;   et al. | 2004-01-22 |
Electronic and optoelectronic component packaging technique App 20040012083 - Farrell, Brian ;   et al. | 2004-01-22 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.