Jayakumar; Nikhil

Patent Applications and Registrations

Patent applications and USPTO patent grants for Jayakumar; Nikhil.The latest application filed is for "system and method to manage power throttling".

Company Profile

2.10.12

Jayakumar; Nikhil - San Jose CA
Jayakumar; Nikhil - Sunnyvale CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
System And Method To Manage Power Throttling App 20220244767 - Sodani; Avinash ; et al.	2022-08-04
System and method to manage power throttling Grant 11,340,673 - Sodani , et al. May 24, 2	2022-05-24
Power Management And Staggering Transitioning From Idle Mode To Operational Mode App 20210318740 - Sripada; Srinivas ; et al.	2021-10-14
Approach for chip-level flop insertion and verification based on logic interface definition Grant 10,303,626 - Wang , et al.	2019-05-28
Baseboard interconnection device, system and method Grant 10,198,389 - Motamedi , et al. Fe	2019-02-05
Determination of flip-flop count in physical design Grant 9,792,400 - Singh , et al. October 17, 2	2017-10-17
Automated flip-flop insertions in physical design without perturbation of routing Grant 9,600,614 - Jayakumar , et al. March 21, 2	2017-03-21
Repeater insertions providing reduced routing perturbation caused by flip-flop insertions Grant 9,600,620 - Ahluwalia , et al. March 21, 2	2017-03-21
Determination Of Flip-flop Count In Physical Design App 20170068769 - SINGH; Chirinjeev ; et al.	2017-03-09
Approach For Chip-level Flop Insertion And Verification Based On Logic Interface Definition App 20160291932 - WANG; Weihuang ; et al.	2016-10-06
Repeater Insertions Providing Reduced Routing Perturbation Caused By Flip-flop Insertions App 20160275230 - AHLUWALIA; Daman ; et al.	2016-09-22
System for and method of placing clock stations using variable drive-strength clock drivers built out of a smaller subset of base cells for hybrid tree-mesh clock distribution networks Grant 9,443,053 - Jayakumar , et al. September 13, 2	2016-09-13
Automated Flip-flop Insertions In Physical Design Without Perturbation Of Routing App 20160224709 - JAYAKUMAR; Nikhil ; et al.	2016-08-04
System for and method of combining CMOS inverters of multiple drive strengths to create tune-able clock inverters of variable drive strengths in hybrid tree-mesh clock distribution networks Grant 9,390,209 - Jayakumar , et al. July 12, 2	2016-07-12
System for and method of tuning clock networks constructed using variable drive-strength clock inverters with variable drive-strength clock drivers built out of a smaller subset of base cells Grant 9,305,129 - Jayakumar , et al. April 5, 2	2016-04-05
Network Device, System And Method Having A Rotated Chip Floorplan App 20160014885 - Motamedi; Amir H. ; et al.	2016-01-14
Baseboard Interconnection Device, System And Method App 20160012006 - Motamedi; Amir H. ; et al.	2016-01-14
System For And Method Of Placing And Routing Clock Stations Using Variable Drive-strength Clock Drivers Built Out Of A Smaller Subset Of Base Cells For Hybrid Tree-mesh Clock Distribution Networks App 20150186589 - Jayakumar; Nikhil ; et al.	2015-07-02
System For And Method Of Combining Cmos Inverters Of Multiple Drive Strengths To Create Tune-able Clock Inverters Of Variable Drive Strengths In Hybrid Tree-mesh Clock Distribution Networks App 20150186560 - Jayakumar; Nikhil ; et al.	2015-07-02
System For And Method Of Tuning Clock Networks Constructed Using Variable Drive-strength Clock Inverters With Variable Drive-strength Clock Drivers Built Out Of A Smaller Subset Of Base Cells App 20150186583 - Jayakumar; Nikhil ; et al.	2015-07-02
Low power reconfigurable circuits with delay compensation Grant 7,880,505 - Khatri , et al. February 1, 2	2011-02-01
Low Power Reconfigurable Circuits With Delay Compensation App 20100213978 - Khatri; Sunil Papanchand ; et al.	2010-08-26

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