loadpatents
name:-0.009303092956543
name:-0.031023025512695
name:-0.003018856048584
Jastrzebski; Lubomir L. Patent Filings

Jastrzebski; Lubomir L.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Jastrzebski; Lubomir L..The latest application filed is for "micro photoluminescence imaging".

Company Profile
2.27.7
  • Jastrzebski; Lubomir L. - Clearwater FL
  • Jastrzebski; Lubomir L. - Plainsboro NJ
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Micro photoluminescence imaging
Grant 10,883,941 - Kiss , et al. January 5, 2
2021-01-05
Micro Photoluminescence Imaging
App 20200300767 - Kiss; Zoltan Tamas ;   et al.
2020-09-24
Micro Photoluminescence Imaging
App 20190391079 - Kiss; Zoltan Tamas ;   et al.
2019-12-26
Micro photoluminescence imaging with optical filtering
Grant 10,209,190 - Kiss , et al. Feb
2019-02-19
Micro Photoluminescence Imaging With Optical Filtering
App 20180313761 - Kiss; Zoltan Tamas ;   et al.
2018-11-01
Micro photoluminescence imaging with optical filtering
Grant 10,018,565 - Kiss , et al. July 10, 2
2018-07-10
Micro photoluminescence imaging
Grant 10,012,593 - Kiss , et al. July 3, 2
2018-07-03
Micro Photoluminescence Imaging
App 20160328840 - Kiss; Zoltan Tamas ;   et al.
2016-11-10
Micro Photoluminescence Imaging With Optical Filtering
App 20160327485 - Kiss; Zoltan Tamas ;   et al.
2016-11-10
Enhanced Sensitivity Non-contact Electrical Monitoring Of Copper Contamination On Silicon Surface
App 20090047748 - Savtchouk; Alexandre ;   et al.
2009-02-19
Determining composition of mixed dielectrics
Grant 6,815,974 - Lagowski , et al. November 9, 2
2004-11-09
Steady state method for measuring the thickness and the capacitance of ultra thin dielectric in the presence of substantial leakage current
Grant 6,680,621 - Savtchouk , et al. January 20, 2
2004-01-20
Steady state method for measuring the thickness and the capacitance of ultra thin dielectric in the presence of substantial leakage current
App 20020125900 - Savtchouk, Alexander ;   et al.
2002-09-12
Method for forming dielectrically isolated transistor
Grant 4,923,826 - Jastrzebski , et al. May 8, 1
1990-05-08
Method for making a silicon-on-insulator substrate
Grant 4,891,092 - Jastrzebski January 2, 1
1990-01-02
High temperature annealing to improve SIMOX characteristics
Grant 4,824,698 - Jastrzebski , et al. April 25, 1
1989-04-25
Method of making integrated circuit with pair of MOS field effect transistors sharing a common source/drain region
Grant 4,772,568 - Jastrzebski September 20, 1
1988-09-20
Optical reflectance method of examining a SIMOX article
Grant 4,766,317 - Harbeke , et al. August 23, 1
1988-08-23
Dielectrically isolated PMOS, NMOS, PNP and NPN transistors on a silicon wafer
Grant 4,751,561 - Jastrzebski June 14, 1
1988-06-14
Recessed oxide method for making a silicon-on-insulator substrate
Grant 4,704,186 - Jastrzebski November 3, 1
1987-11-03
Method of depositing uniformly thick selective epitaxial silicon
Grant 4,698,316 - Corboy, Jr. , et al. October 6, 1
1987-10-06
Fabricating of a CMOS FET with reduced latchup susceptibility
Grant 4,619,033 - Jastrzebski October 28, 1
1986-10-28
Method for forming uniformly thick selective epitaxial silicon
Grant 4,592,792 - Corboy, Jr. , et al. June 3, 1
1986-06-03
Vertical IGFET with internal gate and method for making same
Grant 4,586,240 - Blackstone , et al. May 6, 1
1986-05-06
Method for growing monocrystalline silicon through mask layer
Grant 4,578,142 - Corboy, Jr. , et al. March 25, 1
1986-03-25
CMOS Structure incorporating vertical IGFETS
Grant 4,566,025 - Jastrzebski , et al. January 21, 1
1986-01-21
Method for forming a void-free monocrystalline epitaxial layer on a mask
Grant 4,557,794 - McGinn , et al. December 10, 1
1985-12-10
Vertically integrated IGFET device
Grant 4,554,570 - Jastrzebski , et al. November 19, 1
1985-11-19
Method for growing monocrystalline silicon on a mask layer
Grant 4,549,926 - Corboy, Jr. , et al. October 29, 1
1985-10-29
Vertical IGFET with internal gate and method for making same
Grant 4,546,375 - Blackstone , et al. October 8, 1
1985-10-08
Method for fabricating a self-aligned vertical IGFET
Grant 4,530,149 - Jastrzebski , et al. July 23, 1
1985-07-23
Method to determine the crystalline properties of an interface of two materials by an optical technique
Grant 4,498,772 - Jastrzebski , et al. February 12, 1
1985-02-12
CCD Imagers with substrates having drift field
Grant 4,481,522 - Jastrzebski , et al. November 6, 1
1984-11-06
Semiconductor imagers
Grant 4,348,690 - Jastrzebski , et al. September 7, 1
1982-09-07

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed