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Patent applications and USPTO patent grants for Jasper Design Automation.The latest application filed is for "formal verification of deadlock property".
Patent | Date |
---|---|
Formal verification of deadlock property Grant 8,381,148 - Loh , et al. February 19, 2 | 2013-02-19 |
System and method for determining and identifying signals that are relevantly determined by a selected signal in a circuit design Grant 7,437,694 - Loh , et al. October 14, 2 | 2008-10-14 |
System and method for measuring progress for formal verification of a design using analysis region Grant 7,412,674 - Singhal , et al. August 12, 2 | 2008-08-12 |
System and method for identifying design efficiency and effectiveness parameters for verifying properties of a circuit model Grant 7,159,198 - Ip , et al. January 2, 2 | 2007-01-02 |
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