loadpatents
name:-0.039951801300049
name:-0.025768995285034
name:-0.0064339637756348
JANG; Kiyoun Patent Filings

JANG; Kiyoun

Patent Applications and Registrations

Patent applications and USPTO patent grants for JANG; Kiyoun.The latest application filed is for "electronic device including battery".

Company Profile
5.34.35
  • JANG; Kiyoun - Suwon-si KR
  • JANG; Kiyoun - Gyeonggi-do KR
  • Jang; KiYoun - Kyoungki-do N/A KR
  • Jang; KiYoun - Kyoungiki-do KR
  • Jang; KiYoun - KyungKi-Do KR
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Electronic Device Including Battery
App 20220302545 - JANG; Kiyoun ;   et al.
2022-09-22
Battery And Electronic Device Including Battery
App 20220140403 - KIM; Sunjin ;   et al.
2022-05-05
Battery And Electronic Device Comprising Same
App 20210234203 - JANG; Kiyoun ;   et al.
2021-07-29
Method To Charge Battery And Electronic Device Including Battery
App 20210091586 - JANG; Kiyoun ;   et al.
2021-03-25
Battery And Electronic Device Including Same
App 20210020893 - Jeon; Yongsub ;   et al.
2021-01-21
Electronic Device Including Cooling Function And Controlling Method Thereof
App 20200389996 - JEONG; Chihwan ;   et al.
2020-12-10
Electronic device including cooling function and controlling method thereof
Grant 10,785,887 - Jeong , et al. Sept
2020-09-22
Electronic device having wireless power transmitting/receiving conductive pattern
Grant 10,680,470 - Jang , et al.
2020-06-09
Electronic Device Having Wireless Power Transmitting/receiving Conductive Pattern
App 20190123599 - JANG; Kiyoun ;   et al.
2019-04-25
Electronic device having wireless power transmitting/receiving conductive pattern
Grant 10,158,261 - Jang , et al. Dec
2018-12-18
Semiconductor device and method of forming dummy pillars between semiconductor die and substrate for maintaining standoff distance
Grant 10,096,540 - Lee , et al. October 9, 2
2018-10-09
Electronic Device Including Cooling Function And Controlling Method Thereof
App 20180288898 - Jeong; Chihwan ;   et al.
2018-10-04
Electronic Device Having Wireless Power Transmitting/receiving Conductive Pattern
App 20170047791 - Jang; Kiyoun ;   et al.
2017-02-16
Semiconductor device and method of forming reduced surface roughness in molded underfill for improved C-SAM inspection
Grant 9,460,972 - Park , et al. October 4, 2
2016-10-04
Semiconductor device and method of forming vertically offset bond on trace interconnect structure on leadframe
Grant 9,236,332 - Pagaila , et al. January 12, 2
2016-01-12
Semiconductor device and method of forming conductive protrusion over conductive pillars or bond pads as fixed offset vertical interconnect structure
Grant 9,230,933 - Lee , et al. January 5, 2
2016-01-05
Semiconductor device and method of forming non-linear interconnect layer with extended length for joint reliability
Grant 9,117,812 - Lee , et al. August 25, 2
2015-08-25
Semiconductor die and method of forming sloped surface in photoresist layer to enhance flow of underfill material between semiconductor die and substrate
Grant 9,054,100 - Lee , et al. June 9, 2
2015-06-09
Semiconductor device and method of forming adjacent channel and dam material around die attach area of substrate to control outward flow of underfill material
Grant 9,030,030 - Lee , et al. May 12, 2
2015-05-12
Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrate
Grant 8,896,133 - Cho , et al. November 25, 2
2014-11-25
Semiconductor device with bump formed on substrate to prevent ELK ILD delamination during reflow process
Grant 8,884,339 - Jang , et al. November 11, 2
2014-11-11
Semiconductor Device Having High-Density Interconnect Array with Core Pillars Formed With OSP Coating
App 20140159236 - Kim; BaeYong ;   et al.
2014-06-12
Semiconductor device having vertically offset bond on trace interconnects on recessed and raised bond fingers
Grant 8,742,566 - Jang , et al. June 3, 2
2014-06-03
Semiconductor Device and Method of Forming Non-Linear Interconnect Layer with Extended Length for Joint Reliability
App 20140103503 - Lee; JaeHyun ;   et al.
2014-04-17
Semiconductor device and method of forming non-linear interconnect layer with extended length for joint reliability
Grant 8,642,384 - Lee , et al. February 4, 2
2014-02-04
Semiconductor device and method of forming vertically offset bond on trace interconnects on different height traces
Grant 8,563,418 - Pagaila , et al. October 22, 2
2013-10-22
Semiconductor Device and Method of Forming Bump on Substrate to Prevent ELK ILD Delamination During Reflow Process
App 20130264705 - Jang; KiYoun ;   et al.
2013-10-10
Semiconductor Device and Method of Forming Vertically Offset Conductive Pillars Over First Substrate Aligned to Vertically Offset BOT Interconnect Sites Formed Over Second Substrate
App 20130234324 - Cho; SungWon ;   et al.
2013-09-12
Semiconductor Device and Method of Forming Non-Linear Interconnect Layer with Extended Length for Joint Reliability
App 20130234318 - Lee; JaeHyun ;   et al.
2013-09-12
Semiconductor device including bump formed on substrate to prevent extremely-low dielectric constant (ELK) interlayer dielectric layer (ILD) delamination during reflow process
Grant 8,519,536 - Jang , et al. August 27, 2
2013-08-27
Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrate
Grant 8,492,197 - Cho , et al. July 23, 2
2013-07-23
Semiconductor Device and Method of Forming Reduced Surface Roughness in Molded Underfill for Improved C-SAM Inspection
App 20130175701 - Park; SeongWon ;   et al.
2013-07-11
Semiconductor Device and Method of Forming Vertically Offset Bond on Trace Interconnect Structure on Leadframe
App 20130154067 - Pagaila; Reza A. ;   et al.
2013-06-20
Semiconductor Device and Method of Forming Adjacent Channel and Dam Material Around Die Attach Area of Substrate to Control Outward Flow of Underfill Material
App 20130147065 - Lee; KyungHoon ;   et al.
2013-06-13
Semiconductor Device Having Vertically Offset Bond on Trace Interconnects on Recessed and Raised Bond Fingers
App 20130134586 - Jang; KiYoun ;   et al.
2013-05-30
Semiconductor Die and Method of Forming Sloped Surface in Photoresist Layer to Enhance Flow of Underfill Material Between Semiconductor Die and Substrate
App 20130105967 - Lee; JaeHyun ;   et al.
2013-05-02
Semiconductor Device and Method of Forming Bump on Substrate to Prevent ELK ILD Delamination During Reflow Process
App 20130087913 - Jang; KiYoun ;   et al.
2013-04-11
Semiconductor device and method of forming vertically offset bond on trace interconnect structure on leadframe
Grant 8,409,978 - Pagaila , et al. April 2, 2
2013-04-02
Semiconductor Device and Method of Forming Conductive Protrusions Over Conductive Pillars or Bond Pads as Fixed Offset Vertical Interconnect Structures
App 20130069221 - Lee; JaeHyun ;   et al.
2013-03-21
Semiconductor device and method of forming adjacent channel and DAM material around die attach area of substrate to control outward flow of underfill material
Grant 8,399,300 - Lee , et al. March 19, 2
2013-03-19
Method of forming vertically offset bond on trace interconnects on recessed and raised bond fingers
Grant 8,389,398 - Jang , et al. March 5, 2
2013-03-05
Semiconductor method of forming bump on substrate to prevent ELK ILD delamination during reflow process
Grant 8,367,467 - Jang , et al. February 5, 2
2013-02-05
Semiconductor Device and Method of Forming Dummy Pillars Between Semiconductor Die and Substrate for Maintaining Standoff Distance
App 20120286418 - Lee; KyungHoon ;   et al.
2012-11-15
Semiconductor Device Having Vertically Offset Bond on Trace Interconnects on Recessed and Raised Bond Fingers
App 20120181690 - Jang; KiYoun ;   et al.
2012-07-19
Semiconductor device having vertically offset bond on trace interconnects on recessed and raised bond fingers
Grant 8,169,071 - Jang , et al. May 1, 2
2012-05-01
Semiconductor Device and Method of Forming Vertically Offset Conductive Pillars Over First Substrate Aligned to Vertically Offset BOT Interconnect Sites Formed Over Second Substrate
App 20120043672 - Cho; SungWon ;   et al.
2012-02-23
Semiconductor Device and Method of Forming Vertically Offset Bond on Trace Interconnects on Different Height Traces
App 20120025373 - Pagaila; Reza A. ;   et al.
2012-02-02
Semiconductor Device and Method of Forming Vertically Offset Bond on Trace Interconnect Structure on Leadframe
App 20110316132 - Pagaila; Reza A. ;   et al.
2011-12-29
Semiconductor Device and Method of Forming Bump on Substrate to Prevent ELK ILD Delamination During Reflow Process
App 20110260316 - Jang; KiYoun ;   et al.
2011-10-27
Semiconductor Device and Method of Forming Adjacent Channel and DAM Material Around Die Attach Area of Substrate to Control Outward Flow of Underfill Material
App 20110260338 - Lee; KyungHoon ;   et al.
2011-10-27
Semiconductor device and method of forming vertically offset bond on trace interconnects on different height traces
Grant 8,039,384 - Pagaila , et al. October 18, 2
2011-10-18
Semiconductor Device And Method Of Forming Vertically Offset Bond On Trace Interconnects On Different Height Traces
App 20110221058 - Pagaila; Reza A. ;   et al.
2011-09-15
Semiconductor Device Having Vertically Offset Bond on Trace Interconnects on Recessed and Raised Bond Fingers
App 20110121452 - Jang; KiYoun ;   et al.
2011-05-26
Method of forming vertically offset bond on trace interconnects on recessed and raised bond fingers
Grant 7,897,502 - Jang , et al. March 1, 2
2011-03-01
Semiconductor Device and Method of Forming Vertically Offset Bond on Trace Interconnects on Recessed and Raised Bond Fingers
App 20100059866 - Jang; KiYoun ;   et al.
2010-03-11
Semiconductor Device Having High-Density Interconnect Array with Core Pillars Formed With OSP Coating
App 20090233436 - Kim; BaeYong ;   et al.
2009-09-17

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