| Patent | Date |
|---|
Non-planar I/o And Logic Semiconductor Devices Having Different Workfunction On Common Substrate
App 20220238383 - OLAC-VAW; Roman W. ; et al. | 2022-07-28 |
Semiconductor Device Having Metal Interconnects With Different Thicknesses
App 20220157729 - Phoa; Kinyip ; et al. | 2022-05-19 |
Non-planar I/O and logic semiconductor devices having different workfunction on common substrate
Grant 11,335,601 - Olac-Vaw , et al. May 17, 2 | 2022-05-17 |
Self-aligned gate endcap (SAGE) architecture having endcap plugs
Grant 11,329,138 - Subramanian , et al. May 10, 2 | 2022-05-10 |
High Voltage Three-dimensional Devices Having Dielectric Liners
App 20220130871 - HAFEZ; Walid M. ; et al. | 2022-04-28 |
Non-planar Semiconductor Device Having Omega-fin With Doped Sub-fin Region And Method To Fabricate Same
App 20220130962 - BHIMARASETTI; Gopinath ; et al. | 2022-04-28 |
Dielectric And Isolation Lower Fin Material For Fin-based Electronics
App 20220102488 - HAFEZ; Walid M. ; et al. | 2022-03-31 |
Adjacent Gate-all-around Integrated Circuit Structures Having Non-merged Epitaxial Source Or Drain Regions
App 20220093588 - SUBRAMANIAN; Sairam ; et al. | 2022-03-24 |
Non-planar semiconductor device having omega-fin with doped sub-fin region and method to fabricate same
Grant 11,276,760 - Bhimarasetti , et al. March 15, 2 | 2022-03-15 |
Dual Self-aligned Gate Endcap (sage) Architectures
App 20220077302 - SUBRAMANIAN; Sairam ; et al. | 2022-03-10 |
Unidirectional Self-aligned Gate Endcap (sage) Architectures With Gate-orthogonal Walls
App 20220077145 - HAFEZ; Walid M. ; et al. | 2022-03-10 |
Semiconductor device having metal interconnects with different thicknesses
Grant 11,264,329 - Phoa , et al. March 1, 2 | 2022-03-01 |
High voltage three-dimensional devices having dielectric liners
Grant 11,251,201 - Hafez , et al. February 15, 2 | 2022-02-15 |
Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls
Grant 11,217,582 - Hafez , et al. January 4, 2 | 2022-01-04 |
Dual self-aligned gate endcap (SAGE) architectures
Grant 11,205,708 - Subramanian , et al. December 21, 2 | 2021-12-21 |
Dielectric and isolation lower fin material for fin-based electronics
Grant 11,139,370 - Hafez , et al. October 5, 2 | 2021-10-05 |
Gate Endcap Architectures Having Relatively Short Vertical Stack
App 20210305243 - SUBRAMANIAN; Sairam ; et al. | 2021-09-30 |
Multi voltage threshold transistors through process and design-induced multiple work functions
Grant 11,121,040 - Lee , et al. September 14, 2 | 2021-09-14 |
Transistor with an airgap spacer adjacent to a transistor gate
Grant 11,114,538 - Lee , et al. September 7, 2 | 2021-09-07 |
Hybrid finfet structure with bulk source/drain regions
Grant 11,075,286 - Jan , et al. July 27, 2 | 2021-07-27 |
Resistor between gates in self-aligned gate edge architecture
Grant 10,964,690 - Olac-Vaw , et al. March 30, 2 | 2021-03-30 |
Non-planar I/o And Logic Semiconductor Devices Having Different Workfunction On Common Substrate
App 20210090956 - OLAC-VAW; Roman W. ; et al. | 2021-03-25 |
Dual fin endcap for self-aligned gate edge (SAGE) architectures
Grant 10,950,606 - Hafez , et al. March 16, 2 | 2021-03-16 |
Semiconductor Device Having Metal Interconnects With Different Thicknesses
App 20210074642 - Phoa; Kinyip ; et al. | 2021-03-11 |
Fin-based thin film resistor
Grant 10,930,729 - Jan , et al. February 23, 2 | 2021-02-23 |
Transistor with inner-gate spacer
Grant 10,923,574 - Liu , et al. February 16, 2 | 2021-02-16 |
High Voltage Three-dimensional Devices Having Dielectric Liners
App 20210036026 - HAFEZ; Walid M. ; et al. | 2021-02-04 |
Metal-oxide-polysilicon tunable resistor for flexible circuit design and method of fabricating same
Grant 10,903,372 - Phoa , et al. January 26, 2 | 2021-01-26 |
Metal resistor and self-aligned gate edge (SAGE) architecture having a metal resistor
Grant 10,892,261 - Hafez , et al. January 12, 2 | 2021-01-12 |
Non-planar I/O and logic semiconductor devices having different workfunction on common substrate
Grant 10,892,192 - Olac-Vaw , et al. January 12, 2 | 2021-01-12 |
Self-aligned Gate Endcap (sage) Architecture Having Vertical Transistor With Sage Gate Structure
App 20200411665 - HAFEZ; Walid M. ; et al. | 2020-12-31 |
Variable Pitch And Stack Height For High Performance Interconnects
App 20200411435 - LIU; En-Shao ; et al. | 2020-12-31 |
Isolation well doping with solid-state diffusion sources for finFET architectures
Grant 10,854,607 - Jan , et al. December 1, 2 | 2020-12-01 |
FINFET based junctionless wrap around structure
Grant 10,854,757 - Ramaswamy , et al. December 1, 2 | 2020-12-01 |
High voltage three-dimensional devices having dielectric liners
Grant 10,847,544 - Hafez , et al. November 24, 2 | 2020-11-24 |
Antifuse element using spacer breakdown
Grant 10,847,456 - Chang , et al. November 24, 2 | 2020-11-24 |
Dielectric And Isolation Lower Fin Material For Fin-based Electronics
App 20200335582 - HAFEZ; Walid M. ; et al. | 2020-10-22 |
Monolithic splitter using re-entrant poly silicon waveguides
Grant 10,811,751 - Ramaswamy , et al. October 20, 2 | 2020-10-20 |
Ultra-scaled fin pitch having dual gate dielectrics
Grant 10,784,378 - Hafez , et al. Sept | 2020-09-22 |
High-voltage Transistor With Self-aligned Isolation
App 20200295190 - HAFEZ; Walid M. ; et al. | 2020-09-17 |
Transmission lines using bending fins from local stress
Grant 10,761,264 - Ramaswamy , et al. Sep | 2020-09-01 |
MOS antifuse with void-accelerated breakdown
Grant 10,763,209 - Olac-Vaw , et al. Sep | 2020-09-01 |
High Voltage Three-dimensional Devices Having Dielectric Liners
App 20200273887 - HAFEZ; Walid M. ; et al. | 2020-08-27 |
Non-planar I/o And Logic Semiconductor Devices Having Different Workfunction On Common Substrate
App 20200273752 - OLAC-VAW; Roman W. ; et al. | 2020-08-27 |
Depletion mode gate in ultrathin FINFET based architecture
Grant 10,756,210 - Jan , et al. A | 2020-08-25 |
Dielectric and isolation lower Fin material for Fin-based electronics
Grant 10,741,640 - Hafez , et al. A | 2020-08-11 |
Isolation Well Doping With Solid-state Diffusion Sources For Finfet Architectures
App 20200251471 - Kind Code | 2020-08-06 |
Methods Of Integrating Multiple Gate Dielectric Transistors On A Tri-gate (finfet) Process
App 20200251470 - Kind Code | 2020-08-06 |
High-voltage transistor with self-aligned isolation
Grant 10,707,346 - Hafez , et al. | 2020-07-07 |
Non-planar I/O and logic semiconductor devices having different workfunction on common substrate
Grant 10,692,771 - Olac-Vaw , et al. | 2020-06-23 |
High voltage three-dimensional devices having dielectric liners
Grant 10,692,888 - Hafez , et al. | 2020-06-23 |
Metal-oxide-polysilicon Tunable Resistor For Flexible Circuit Design And Method Of Fabricating Same
App 20200194599 - PHOA; Kinyip ; et al. | 2020-06-18 |
Methods of integrating multiple gate dielectric transistors on a tri-gate (FINFET) process
Grant 10,658,361 - Tsai , et al. | 2020-05-19 |
Doping with solid-state diffusion sources for finFET architectures
Grant 10,643,999 - Jan , et al. | 2020-05-05 |
Cost Effective Precision Resistor Using Blocked Depop Method In Self-aligned Gate Endcap (sage) Architecture
App 20200105746 - OLAC-VAW; Roman ; et al. | 2020-04-02 |
Ultra-scaled Fin Pitch Processes Having Dual Gate Dielectrics And The Resulting Structures
App 20200066897 - HAFEZ; Walid M. ; et al. | 2020-02-27 |
Metal Resistor And Self-aligned Gate Edge (sage) Architecture Having A Metal Resistor
App 20200066712 - HAFEZ; Walid M. ; et al. | 2020-02-27 |
Depletion Mode Gate In Ultrathin Finfet Based Architecture
App 20200066907 - JAN; Chia-Hong ; et al. | 2020-02-27 |
Transistor with thermal performance boost
Grant 10,559,688 - Lee , et al. Feb | 2020-02-11 |
Resistor Between Gates In Self-aligned Gate Edge Architecture
App 20200043914 - OLAC-VAW; ROMAN W. ; et al. | 2020-02-06 |
Transistor with dual-gate spacer
Grant 10,535,747 - Liu , et al. Ja | 2020-01-14 |
Transistor With Inner-gate Spacer
App 20200006509 - LIU; EN-SHAO ; et al. | 2020-01-02 |
Monolithic Splitter Using Re-entrant Poly Silicon Waveguides
App 20190356032 - RAMASWAMY; Rahul ; et al. | 2019-11-21 |
Dual Self-aligned Gate Endcap (sage) Architectures
App 20190305112 - SUBRAMANIAN; Sairam ; et al. | 2019-10-03 |
Multi Voltage Threshold Transistors Through Process And Design-induced Multiple Work Functions
App 20190304840 - LEE; Chen-Guan ; et al. | 2019-10-03 |
Unidirectional Self-aligned Gate Endcap (sage) Architectures With Gate-orthogonal Walls
App 20190304971 - HAFEZ; Walid M. ; et al. | 2019-10-03 |
Self-aligned Gate Endcap (sage) Architecture Having Endcap Plugs
App 20190305111 - SUBRAMANIAN; Sairam ; et al. | 2019-10-03 |
Transistor with inner-gate spacer
Grant 10,431,661 - Liu , et al. O | 2019-10-01 |
Non-planar Semiconductor Device Having Omega-fin With Doped Sub-fin Region And Method To Fabricate Same
App 20190296114 - BHIMARASETTI; Gopinath ; et al. | 2019-09-26 |
Dielectric And Isolation Lower Fin Material For Fin-based Electronics
App 20190296105 - HAFEZ; Walid M. ; et al. | 2019-09-26 |
Doping With Solid-state Diffusion Sources For Finfet Architectures
App 20190287973 - Jan; Chia-Hong ; et al. | 2019-09-19 |
Dual Fin Endcap For Self-aligned Gate Edge (sage) Architectures
App 20190287972 - HAFEZ; Walid M. ; et al. | 2019-09-19 |
Transmission Lines Using Bending Fins From Local Stress
App 20190278022 - RAMASWAMY; Rahul ; et al. | 2019-09-12 |
Finfet Based Junctionless Wrap Around Structure
App 20190245098 - RAMASWAMY; Rahul ; et al. | 2019-08-08 |
Hybrid Finfet Structure With Bulk Source/drain Regions
App 20190237564 - JAN; Chia-Hong ; et al. | 2019-08-01 |
Dielectric and isolation lower Fin material for Fin-based electronics
Grant 10,355,081 - Hafez , et al. July 16, 2 | 2019-07-16 |
Non-planar semiconductor device having omega-fin with doped sub-fin region and method to fabricate same
Grant 10,355,093 - Bhimarasetti , et al. July 16, 2 | 2019-07-16 |
Fin-based Thin Film Resistor
App 20190206980 - JAN; Chia-Hong ; et al. | 2019-07-04 |
Compound lateral resistor structures for integrated circuitry
Grant 10,340,220 - Lee , et al. | 2019-07-02 |
Doping with solid-state diffusion sources for finFET architectures
Grant 10,340,273 - Jan , et al. | 2019-07-02 |
Monolithic integration of high voltage transistors and low voltage non-planar transistors
Grant 10,312,367 - Phoa , et al. | 2019-06-04 |
Dual height glass for finFET doping
Grant 10,304,681 - Lee , et al. | 2019-05-28 |
Non-planar I/o And Logic Semiconductor Devices Having Different Workfunction On Common Substrate
App 20190157153 - OLAC-VAW; Roman W. ; et al. | 2019-05-23 |
Transistor With Airgap Spacer
App 20190123164 - Lee; Chen-Guan ; et al. | 2019-04-25 |
Vertical non-planar semiconductor device for system-on-chip (SoC) applications
Grant 10,263,112 - Jan , et al. | 2019-04-16 |
Non-linear Fin-based Devices
App 20190097057 - Dias; Neville L. ; et al. | 2019-03-28 |
Pillar resistor structures for integrated circuitry
Grant 10,243,034 - Lee , et al. | 2019-03-26 |
Non-planar I/O and logic semiconductor devices having different workfunction on common substrate
Grant 10,229,853 - Olac-Vaw , et al. | 2019-03-12 |
Harvesting Energy In An Integrated Circuit Using The Seebeck Effect
App 20190051806 - Phoa; Kinyip ; et al. | 2019-02-14 |
Transistor with airgap spacer
Grant 10,204,999 - Lee , et al. Feb | 2019-02-12 |
Transistor gate metal with laterally graduated work function
Grant 10,192,969 - Jan , et al. Ja | 2019-01-29 |
Transistor With Thermal Performance Boost
App 20190027604 - LEE; CHEN-GUAN ; et al. | 2019-01-24 |
Compound Lateral Resistor Structures For Integrated Circuitry
App 20190006279 - Lee; Chen-Guan ; et al. | 2019-01-03 |
Transistor With Dual-gate Spacer
App 20180374927 - LIU; EN-SHAO ; et al. | 2018-12-27 |
Non-linear fin-based devices
Grant 10,164,115 - Dias , et al. Dec | 2018-12-25 |
Through silicon via based photovoltaic cell
Grant 10,158,034 - Phoa , et al. Dec | 2018-12-18 |
Transistor With Inner-gate Spacer
App 20180350932 - LIU; EN-SHAO ; et al. | 2018-12-06 |
Dual Threshold Voltage (vt) Channel Devices And Their Methods Of Fabrication
App 20180323260 - CHANG; Hsu-Yu ; et al. | 2018-11-08 |
Planar device on fin-based transistor architecture
Grant 10,115,721 - Hafez , et al. October 30, 2 | 2018-10-30 |
Methods of integrating multiple gate dielectric transistors on a tri-gate (finFET) process
Grant 10,096,599 - Tsai , et al. October 9, 2 | 2018-10-09 |
Isolation well doping with solid-state diffusion sources for FinFET architectures
Grant 10,090,304 - Jan , et al. October 2, 2 | 2018-10-02 |
High-voltage Transistor With Self-aligned Isolation
App 20180248039 - HAFEZ; WALID M. ; et al. | 2018-08-30 |
High Voltage Three-dimensional Devices Having Dielectric Liners
App 20180226432 - HAFEZ; Walid M. ; et al. | 2018-08-09 |
Antifuse Element Using Spacer Breakdown
App 20180218977 - CHANG; TING ; et al. | 2018-08-02 |
Transistor With Airgap Spacer
App 20180197966 - Lee; Chen-Guan ; et al. | 2018-07-12 |
Antifuse with backfilled terminals
Grant 10,020,313 - Lee , et al. July 10, 2 | 2018-07-10 |
Embedded fuse with conductor backfill
Grant 10,008,445 - Lee , et al. June 26, 2 | 2018-06-26 |
Fin-based semiconductor devices and methods
Grant 10,002,954 - Hafez , et al. June 19, 2 | 2018-06-19 |
Dielectric And Isolation Lower Fin Material For Fin-based Electronics
App 20180158906 - HAFEZ; Walid M. ; et al. | 2018-06-07 |
Controlled Modification Of Antifuse Programming Voltage
App 20180145083 - TONG; Xiaoghong ; et al. | 2018-05-24 |
Methods of forming tuneable temperature coefficient FR embedded resistors
Grant 9,972,616 - Hafez , et al. May 15, 2 | 2018-05-15 |
High voltage three-dimensional devices having dielectric liners
Grant 9,972,642 - Hafez , et al. May 15, 2 | 2018-05-15 |
Dual Height Glass For Finfet Doping
App 20180114695 - LEE; Chen-Guan ; et al. | 2018-04-26 |
Pillar Resistor Structures For Integrated Circuitry
App 20180108727 - LEE; Chen-Guan ; et al. | 2018-04-19 |
Multi-gate transistor with variably sized fin
Grant 9,947,585 - Nidhi , et al. April 17, 2 | 2018-04-17 |
Antifuse element using spacer breakdown
Grant 9,929,090 - Chang , et al. March 27, 2 | 2018-03-27 |
Extended-drain structures for high voltage field effect transistors
Grant 9,911,815 - Nidhi , et al. March 6, 2 | 2018-03-06 |
Dielectric and isolation lower fin material for fin-based electronics
Grant 9,899,472 - Hafez , et al. February 20, 2 | 2018-02-20 |
High Voltage Three-dimensional Devices Having Dielectric Liners
App 20180040637 - HAFEZ; Walid M. ; et al. | 2018-02-08 |
CMOS-compatible polycide fuse structure and method of fabricating same
Grant 9,881,927 - Yeh , et al. January 30, 2 | 2018-01-30 |
High-voltage transistor architectures, processes of forming same, and systems containing same
Grant 9,865,695 - Hafez , et al. January 9, 2 | 2018-01-09 |
Solid-source diffused junction for fin-based electronics
Grant 9,842,944 - Hafez , et al. December 12, 2 | 2017-12-12 |
High voltage three-dimensional devices having dielectric liners
Grant 9,806,095 - Hafez , et al. October 31, 2 | 2017-10-31 |
Memory cell having isolated charge sites and method of fabricating same
Grant 9,799,668 - Chang , et al. October 24, 2 | 2017-10-24 |
Field effect transistor structure with abrupt source/drain junctions
Grant 9,793,373 - Murthy , et al. October 17, 2 | 2017-10-17 |
Transistor architecture having extended recessed spacer and source/drain regions and method of making same
Grant 9,786,783 - Hafez , et al. October 10, 2 | 2017-10-10 |
Non-planar semiconductor device having self-aligned fin with top blocking layer
Grant 9,780,217 - Yeh , et al. October 3, 2 | 2017-10-03 |
Pillar resistor structures for integrated circuitry
Grant 9,748,327 - Lee , et al. August 29, 2 | 2017-08-29 |
Antifuse element utilizing non-planar topology
Grant 9,748,252 - Hafez , et al. August 29, 2 | 2017-08-29 |
Low leakage non-planar access transistor for embedded dynamic random access memory (eDRAM)
Grant 9,741,721 - Park , et al. August 22, 2 | 2017-08-22 |
Transistor Gate Metal With Laterally Graduated Work Function
App 20170207312 - Jan; Chia-Hong ; et al. | 2017-07-20 |
Field Effect Transistor Structure With Abrupt Source/drain Junctions
App 20170186855 - Murthy; Anand S. ; et al. | 2017-06-29 |
Mos Antifuse With Void-accelerated Breakdown
App 20170162503 - OLAC-VAW; Roman ; et al. | 2017-06-08 |
Pillar Resistor Structures For Integrated Circuitry
App 20170162646 - LEE; Chen-Guan ; et al. | 2017-06-08 |
Through Silicon Via Based Photovoltaic Cell
App 20170155004 - PHOA; KINYIP ; et al. | 2017-06-01 |
Dielectric And Isolation Lower Fin Material For Fin-based Electronics
App 20170133461 - HAFEZ; Walid M. ; et al. | 2017-05-11 |
Doping With Solid-state Diffusion Sources For Finfet Architectures
App 20170125419 - Jan; Chia-Hong ; et al. | 2017-05-04 |
Field effect transistor structure with abrupt source/drain junctions
Grant 9,640,634 - Murthy , et al. May 2, 2 | 2017-05-02 |
Multi-gate Transistor With Variably Sized Fin
App 20170103923 - NIDHI; NIDHI ; et al. | 2017-04-13 |
Non-linear Fin-based Devices
App 20170098709 - DIAS; NEVILLE L. ; et al. | 2017-04-06 |
Extended-drain Structures For High Voltage Field Effect Transistors
App 20170092726 - Nidhi; Nidhi ; et al. | 2017-03-30 |
Vertical Non-planar Semiconductor Device For System-on-chip (soc) Applications
App 20170069758 - Jan; Chia-Hong ; et al. | 2017-03-09 |
Non-planar Semiconductor Device Having Omega-fin With Doped Sub-fin Region And Method To Fabricate Same
App 20170069725 - BHIMARASETTI; GOPINATH ; et al. | 2017-03-09 |
High voltage three-dimensional devices having dielectric liners
Grant 9,570,467 - Hafez , et al. February 14, 2 | 2017-02-14 |
Monolithic Integration Of High Voltage Transistors & Low Voltage Non-planar Transistors
App 20170025533 - Phoa; Kinyip ; et al. | 2017-01-26 |
Solid-source Diffused Junction For Fin-based Electronics
App 20170018658 - HAFEZ; Walid M. ; et al. | 2017-01-19 |
Fin-based Semiconductor Devices And Methods
App 20170005187 - Hafez; Walid M. ; et al. | 2017-01-05 |
Vertical non-planar semiconductor device for system-on-chip (SoC) applications
Grant 9,520,494 - Jan , et al. December 13, 2 | 2016-12-13 |
Antifuse Element Using Spacer Breakdown
App 20160351498 - CHANG; TING ; et al. | 2016-12-01 |
Antifuse With Backfilled Terminals
App 20160336332 - LEE; Chen Guan ; et al. | 2016-11-17 |
Embedded Fuse With Conductor Backfill
App 20160329282 - Lee; Chen-Guan ; et al. | 2016-11-10 |
Planar Device On Fin-based Transistor Architecture
App 20160276346 - HAFEZ; WALID M. ; et al. | 2016-09-22 |
Non-Planar I/O and Logic Semiconductor Devices having Different Workfunction on Common Substrate
App 20160225671 - OLAC-VAW; ROMAN W. ; et al. | 2016-08-04 |
Isolation Well Doping With Solid-state Diffusion Sources For Finfet Architectures
App 20160211262 - JAN; CHIA-HONG ; et al. | 2016-07-21 |
Vertical Non-Planar Semiconductor Device for System-on-Chip (SoC) Applications
App 20160211369 - JAN; CHIA-HONG ; et al. | 2016-07-21 |
Low Leakage Non-Planar Access Transistor for Embedded Dynamic Random Access Memory (eDRAM)
App 20160197082 - PARK; JOODONG ; et al. | 2016-07-07 |
Methods Of Forming Tuneable Temperature Coefficient Fr Embedded Resistors
App 20160181241 - Hafez; Walid ; et al. | 2016-06-23 |
Planar device on fin-based transistor architecture
Grant 9,356,023 - Hafez , et al. May 31, 2 | 2016-05-31 |
Metal fuse by topology
Grant 9,324,665 - Lee , et al. April 26, 2 | 2016-04-26 |
High Voltage Three-dimensional Devices Having Dielectric Liners
App 20160111449 - Hafez; Walid M. ; et al. | 2016-04-21 |
Methods Of Integrating Multiple Gate Dielectric Transistors On A Tri-gate (finfet) Process
App 20160111426 - TSAI; Curtis ; et al. | 2016-04-21 |
Non-planar Semiconductor Device Having Self-aligned Fin With Top Blocking Layer
App 20160056293 - YEH; JENG-YA D. ; et al. | 2016-02-25 |
Cmos-compatible Polycide Fuse Structure And Method Of Fabricating Same
App 20160056162 - YEH; JENG-YA D. ; et al. | 2016-02-25 |
Memory Cell Having Isolated Charge Sites And Method Of Fabricating Same
App 20160049418 - CHANG; TING ; et al. | 2016-02-18 |
Antifuse Element Utilizing Non-planar Topology
App 20160035735 - HAFEZ; WALID M. ; et al. | 2016-02-04 |
Antifuse element utilizing non-planar topology
Grant 9,159,734 - Hafez , et al. October 13, 2 | 2015-10-13 |
High-Voltage Transistor Architectures, Processes of Forming Same, and Systems Containing Same
App 20150206948 - Hafez; Walid M. ; et al. | 2015-07-23 |
Metal Fuse By Topology
App 20150187709 - Lee; Chen-Guan ; et al. | 2015-07-02 |
High Voltage Three-dimensional Devices Having Dielectric Liners
App 20150179525 - Hafez; Walid M. ; et al. | 2015-06-25 |
High-voltage transistor architectures, processes of forming same, and systems containing same
Grant 8,993,401 - Hafez , et al. March 31, 2 | 2015-03-31 |
High voltage three-dimensional devices having dielectric liners
Grant 8,981,481 - Hafez , et al. March 17, 2 | 2015-03-17 |
Precision resistor for non-planar semiconductor device architecture
Grant 8,889,508 - Yeh , et al. November 18, 2 | 2014-11-18 |
Methods Of Integrating Multiple Gate Dielectric Transistors On A Tri-gate (finfet) Process
App 20140319623 - Tsai; Curtis ; et al. | 2014-10-30 |
Precision Resistor For Non-planar Semiconductor Device Architecture
App 20140308785 - Yeh; Jeng-Ya D. ; et al. | 2014-10-16 |
Planar Device On Fin-based Transistor Architecture
App 20140291766 - Hafez; Walid M. ; et al. | 2014-10-02 |
Transistor Architecture Having Extended Recessed Spacer And Source/drain Regions And Method Of Making Same
App 20140291737 - Hafez; Walid M. ; et al. | 2014-10-02 |
Precision resistor for non-planar semiconductor device architecture
Grant 8,796,772 - Yeh , et al. August 5, 2 | 2014-08-05 |
Penetrating implant for forming a semiconductor device
Grant 8,741,720 - Curello , et al. June 3, 2 | 2014-06-03 |
Precision Resistor For Non-planar Semiconductor Device Architecture
App 20140084381 - Yeh; Jeng-Ya D. ; et al. | 2014-03-27 |
Programmable/re-programmable device in high-k metal gate MOS
Grant 8,681,573 - Hafez , et al. March 25, 2 | 2014-03-25 |
Multi-gate transistors
Grant 8,669,617 - Jan , et al. March 11, 2 | 2014-03-11 |
High Voltage Three-dimensional Devices Having Dielectric Liners
App 20140001569 - Hafez; Walid M. ; et al. | 2014-01-02 |
High-Voltage Transistor Architectures, Processes Of Forming Same, And Systems Containing Same
App 20130288444 - Hafez; Walid M. ; et al. | 2013-10-31 |
Antifuse Element Utilizing Non-planar Topology
App 20130270559 - Hafez; Walid M. ; et al. | 2013-10-17 |
Programmable/re-programmable Device In High-k Metal Gate Mos
App 20130229882 - Hafez; Walid M. ; et al. | 2013-09-05 |
High-voltage transistor architectures, processes of forming same, and systems containing same
Grant 8,487,376 - Hafez , et al. July 16, 2 | 2013-07-16 |
Memory cell using BTI effects in high-k metal gate MOS
Grant 8,432,751 - Hafez , et al. April 30, 2 | 2013-04-30 |
Penetrating implant for forming a semiconductor device
Grant 8,426,927 - Curello , et al. April 23, 2 | 2013-04-23 |
Memory Cell Using Bti Effects In High-k Metal Gate Mos
App 20120163103 - Hafez; Walid M. ; et al. | 2012-06-28 |
Multi-gate Transistors
App 20120161237 - Jan; Chia-Hong ; et al. | 2012-06-28 |
Selective spacer formation on transistors of different classes on the same device
Grant 8,174,060 - Curello , et al. May 8, 2 | 2012-05-08 |
Selective spacer formation on transistors of different classes on the same device
Grant 8,154,067 - Curello , et al. April 10, 2 | 2012-04-10 |
High-voltage Transistor Architectures, Processes Of Forming Same, And Systems Containing Same
App 20120043609 - Hafez; Walid M. ; et al. | 2012-02-23 |
Method of forming programmable anti-fuse element
Grant 8,101,471 - Hafez , et al. January 24, 2 | 2012-01-24 |
Penetrating Implant For Forming A Semiconductor Device
App 20110215422 - Curello; Giuseppe ; et al. | 2011-09-08 |
Selective Spacer Formation On Transistors Of Different Classes On The Same Device
App 20110157854 - Curello; Giuseppe ; et al. | 2011-06-30 |
Penetrating implant for forming a semiconductor device
Grant 7,943,468 - Curello , et al. May 17, 2 | 2011-05-17 |
Non-planar embedded polysilicon resistor
App 20100327370 - Jan; Chia-Hong ; et al. | 2010-12-30 |
Programmable fuse and anti-fuse elements and methods of changing conduction states of same
App 20100164603 - Hafez; Walid M. ; et al. | 2010-07-01 |
Flash Cell with Integrated High-K Dielectric and Metal-Based Control Gate
App 20100163952 - Jan; Chia-Hong ; et al. | 2010-07-01 |
Implant process for blocked salicide poly resistor and structures formed thereby
App 20100164001 - Park; Joodong ; et al. | 2010-07-01 |
Field Effect Transistor Structure With Abrupt Source/drain Junctions
App 20100133595 - Murthy; Anand S. ; et al. | 2010-06-03 |
Dual layer hard mask for block salicide poly resistor (BSR) patterning
Grant 7,691,718 - Park , et al. April 6, 2 | 2010-04-06 |
Field effect transistor structure with abrupt source/drain junctions
Grant 7,682,916 - Murthy , et al. March 23, 2 | 2010-03-23 |
Penetrating Implant For Forming A Semiconductor Device
App 20090242998 - Curello; Giuseppe ; et al. | 2009-10-01 |
Selective Spacer Formation On Transistors Of Different Classes On The Same Device
App 20090189193 - CURELLO; GIUSEPPE ; et al. | 2009-07-30 |
Active region spacer for semiconductor devices and method to form the same
Grant 7,560,780 - Curello , et al. July 14, 2 | 2009-07-14 |
Dual layer hard mask for block salicide poly resistor (BSR) patterning
App 20090170273 - Park; Joodong ; et al. | 2009-07-02 |
Selective spacer formation on transistors of different classes on the same device
Grant 7,541,239 - Curello , et al. June 2, 2 | 2009-06-02 |
Field effect transistor structure with abrupt source/drain junctions
App 20090011565 - Murthy; Anand S. ; et al. | 2009-01-08 |
Method of fabricating a field effect transistor structure with abrupt source/drain junctions
Grant 7,436,035 - Murthy , et al. October 14, 2 | 2008-10-14 |
Method of fabricating a field effect transistor structure with abrupt source/drain junctions
Grant 7,338,873 - Murthy , et al. March 4, 2 | 2008-03-04 |
Active region spacer for semiconductor devices and method to form the same
App 20070132057 - Curello; Giuseppe ; et al. | 2007-06-14 |
Device having recessed spacers for improved salicide resistance on polysilicon gates
Grant 7,211,872 - Jan , et al. May 1, 2 | 2007-05-01 |
Concentration-graded alloy sputtering target
App 20060219546 - Jan; Chia-Hong ; et al. | 2006-10-05 |
Method of fabricating a field effect transistor structure with abrupt source/drain junctions
App 20060220153 - Murthy; Anand S. ; et al. | 2006-10-05 |
Structure and manufacturing process of localized shunt to reduce electromigration failure of copper dual damascene process
Grant 7,115,502 - Jan October 3, 2 | 2006-10-03 |
Enhancing adhesion of silicon nitride films to carbon-containing oxide films
Grant 7,071,129 - Jan , et al. July 4, 2 | 2006-07-04 |
Substantially void free interconnect formation
App 20050285269 - Cao, Yang ; et al. | 2005-12-29 |
Interconnect adapted for reduced electron scattering
App 20050224980 - Leu, Jihperng ; et al. | 2005-10-13 |
Structure and manufacturing process of localized shunt to reduce electromigration failure of copper dual damascene process
App 20050191411 - Jan, Chia-Hong | 2005-09-01 |
Method of fabricating a field effect transistor structure with abrupt source/drain junctions
Grant 6,887,762 - Murthy , et al. May 3, 2 | 2005-05-03 |
Structure and manufacturing process of localized shunt to reduce electromigration failure of copper dual damascene process
Grant 6,861,758 - Jan March 1, 2 | 2005-03-01 |
Method of fabricating a field effect transistor structure with abrupt source/drain junctions
App 20050012146 - Murthy, Anand S. ; et al. | 2005-01-20 |
Device structure and method for reducing silicide encroachment
Grant 6,777,759 - Chau , et al. August 17, 2 | 2004-08-17 |
Device with recessed thin and thick spacers for improved salicide resistance on polysilicon gates
Grant 6,777,760 - Jan , et al. August 17, 2 | 2004-08-17 |
Device structure and method for reducing silicide encroachment
Grant 6,765,273 - Chau , et al. July 20, 2 | 2004-07-20 |
Enhancing adhesion of silicon nitride films to carbon-containing oxide films
App 20040051176 - Jan, Chia-Hong ; et al. | 2004-03-18 |
Polysilicon/amorphous silicon composite gate electrode
Grant 6,703,672 - Brigham , et al. March 9, 2 | 2004-03-09 |
Structure and manufacturing process of localized shunt to reduce electromigration failure of copper dual damascene process
App 20040041273 - Jan, Chia-Hong | 2004-03-04 |
Method and device for improved salicide resistance on polysilicon gates
Grant 6,593,633 - Jan , et al. July 15, 2 | 2003-07-15 |
Device having spacers for improved salicide resistance on polysilicon gates
Grant 6,521,964 - Jan , et al. February 18, 2 | 2003-02-18 |
Device structure and method for reducing silicide encroachment
Grant 6,518,155 - Chau , et al. February 11, 2 | 2003-02-11 |
Device having thin first spacers and partially recessed thick second spacers for improved salicide resistance on polysilicon gates
Grant 6,509,618 - Jan , et al. January 21, 2 | 2003-01-21 |
Method of recessing spacers to improved salicide resistance on polysilicon gates
Grant 6,506,652 - Jan , et al. January 14, 2 | 2003-01-14 |
Method for making a dual damascene interconnect using a multilayer hard mask
Grant 6,479,391 - Morrow , et al. November 12, 2 | 2002-11-12 |
Method for making a dual damascene interconnect using a multilayer hard mask
App 20020081854 - Morrow, Patrick ; et al. | 2002-06-27 |
A Device With Thin Spacers To Improve Salicide Resistance On Polysilicon Gates
App 20020082624 - Jan, Chia-Hong ; et al. | 2002-06-27 |
Device structure and method for reducing silicide encroachment
App 20020053711 - Chau, Robert S. ; et al. | 2002-05-09 |
A Device Having Thin First Spacers And Partially Recessed Thick Second Spacers For Improved Salicide Resistance On Polysilicon Gates
App 20020003268 - JAN, CHIA-HONG ; et al. | 2002-01-10 |
Transistor with ultra shallow tip and method of fabrication
Grant 6,326,664 - Chau , et al. December 4, 2 | 2001-12-04 |
A Method Of Recessing Spacers To Improve Salicides Resistance On Polysilicon Gates
App 20010045607 - JAN, CHIA-HONG ; et al. | 2001-11-29 |
Method And Device For Improved Salicide Resistance On Polysilicon Gates
App 20010045586 - JAN, CHIA-HONG ; et al. | 2001-11-29 |
Method and device for improved salicide resistance on polysilicon gates
Grant 6,268,254 - Jan , et al. July 31, 2 | 2001-07-31 |
Semiconductor device having deposited silicon regions and a method of fabrication
Grant 6,235,568 - Murthy , et al. May 22, 2 | 2001-05-22 |
Transistor with minimal junction capacitance and method of fabrication
Grant 6,198,142 - Chau , et al. March 6, 2 | 2001-03-06 |
Transistor with low resistance tip and method of fabrication in a CMOS process
Grant 6,165,826 - Chau , et al. December 26, 2 | 2000-12-26 |
Method of fabricating a MOS transistor with a raised source/drain extension
Grant 6,121,100 - Andideh , et al. September 19, 2 | 2000-09-19 |
Method of forming a transistor
Grant 5,908,313 - Chau , et al. June 1, 1 | 1999-06-01 |
Manufacturable dielectric formed using multiple oxidation and anneal steps
Grant 5,891,809 - Chau , et al. April 6, 1 | 1999-04-06 |
Transistor with ultra shallow tip and method of fabrication
Grant 5,710,450 - Chau , et al. January 20, 1 | 1998-01-20 |
Process for preparing schottky diode contacts with predetermined barrier heights
Grant 5,516,725 - Chang , et al. May 14, 1 | 1996-05-14 |
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