Jamshidi; Shahram
Patent Applications and Registrations
Patent applications and USPTO patent grants for Jamshidi; Shahram.The latest application filed is for "domino circuit with disable feature".
- Jamshidi; Shahram - Cupertino CA
- Jamshidi; Shahram - Santa Clara CA
| Patent | Date |
|---|---|
| Domino circuit with disable feature Grant 7,592,840 - Sit , et al. September 22, 2 | 2009-09-22 |
| Domino Circuit With Disable Feature App 20080106302 - Sit; Kin Yip ; et al. | 2008-05-08 |
| Leakage control in integrated circuits Grant 7,302,652 - Chen , et al. November 27, 2 | 2007-11-27 |
| Gate-clocked domino circuits with reduced leakage current Grant 6,952,118 - Jamshidi , et al. October 4, 2 | 2005-10-04 |
| Word line transistor stacking for leakage control Grant 6,914,848 - Jamshidi , et al. July 5, 2 | 2005-07-05 |
| Word line transistor stacking for leakage control App 20040252574 - Jamshidi, Shahram ; et al. | 2004-12-16 |
| Leakage control in integrated circuits App 20040194037 - Chen, Zhanping ; et al. | 2004-09-30 |
| Gate-clocked domino circuits with reduced leakage current App 20040119503 - Jamshidi, Shahram ; et al. | 2004-06-24 |
| Differential, low voltage swing reducer Grant 6,732,136 - Chen , et al. May 4, 2 | 2004-05-04 |
| Low power entry latch to interface static logic with dynamic logic Grant 6,707,318 - Kumar , et al. March 16, 2 | 2004-03-16 |
| Low power entry latch to interface static logic with dynamic logic App 20030184344 - Kumar, Sudarshan ; et al. | 2003-10-02 |
| Plurality of distinct multiplexers that operate as a single multiplexer Grant 5,646,558 - Jamshidi July 8, 1 | 1997-07-08 |
| High speed reduced area multiplexer Grant 5,598,114 - Jamshidi January 28, 1 | 1997-01-28 |
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