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name:-0.062633991241455
name:-0.069218873977661
name:-0.0014259815216064
Jamil; Sujat Patent Filings

Jamil; Sujat

Patent Applications and Registrations

Patent applications and USPTO patent grants for Jamil; Sujat.The latest application filed is for "apparatus and method for avoiding conflicting entries in a storage structure".

Company Profile
1.76.50
  • Jamil; Sujat - Gilbert AZ
  • Jamil; Sujat - Austin TX US
  • Jamil; Sujat - Chandler AZ
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Interconnected ring network in a multi-processor system
Grant 10,230,542 - Joshua , et al.
2019-03-12
Apparatus and method for avoiding conflicting entries in a storage structure
Grant 10,083,126 - Bryant , et al. September 25, 2
2018-09-25
Apparatus And Method For Avoiding Conflicting Entries In A Storage Structure
App 20180157601 - BRYANT; Richard F. ;   et al.
2018-06-07
Method and apparatus to use hardware alias detection and management in a virtually indexed physically tagged cache
Grant 9,934,152 - Bryant , et al. April 3, 2
2018-04-03
Method and apparatus for use of a preload instruction to improve efficiency of cache
Grant 9,892,051 - Jamil , et al. February 13, 2
2018-02-13
Managing aliasing in a virtually indexed physically tagged cache
Grant 9,842,051 - Schuttenberg , et al. December 12, 2
2017-12-12
Interconnected Ring Network In A Multi-processor System
App 20170180156 - Joshua; Eitan ;   et al.
2017-06-22
Method and apparatus for sharing instruction scheduling resources among a plurality of execution threads in a multi-threaded processor architecture
Grant 9,606,800 - Hameenanttila , et al. March 28, 2
2017-03-28
Interconnected ring network in a multi-processor system
Grant 9,454,480 - Joshua , et al. September 27, 2
2016-09-27
Method and apparatus for processing speculative, out-of-order memory access instructions
Grant 9,442,735 - Jamil , et al. September 13, 2
2016-09-13
Thread-aware cache memory management
Grant 9,223,709 - O'Bleness , et al. December 29, 2
2015-12-29
Systems and methods for reducing interrupt latency
Grant 9,116,742 - Schuttenberg , et al. August 25, 2
2015-08-25
Method and apparatus for associating requests and responses with identification information
Grant 9,086,976 - O'Bleness , et al. July 21, 2
2015-07-21
Method and apparatus having a snoop filter decoupled from an associated cache and a buffer for replacement line addresses
Grant 9,058,272 - O'Bleness , et al. June 16, 2
2015-06-16
Detecting and reissuing of loop instructions in reorder structure
Grant 9,026,769 - Jamil , et al. May 5, 2
2015-05-05
Cache memory bank selection
Grant 8,990,505 - Jamil , et al. March 24, 2
2015-03-24
Method and apparatus for improving cache efficiency
Grant 8,943,273 - Jamil , et al. January 27, 2
2015-01-27
Speculative scheduling of memory instructions in out-of-order processor based on addressing mode comparison
Grant 8,918,625 - O'Bleness , et al. December 23, 2
2014-12-23
Dynamic pipeline reconfiguration including changing a number of stages
Grant 8,806,181 - O'Bleness , et al. August 12, 2
2014-08-12
Interconnected Ring Network In A Multi-processor System
App 20140201326 - Joshua; Eitan ;   et al.
2014-07-17
Interconnected Ring Network In A Multi-processor System
App 20140201445 - Joshua; Eitan ;   et al.
2014-07-17
Programmable cache access protocol to optimize power consumption and performance
Grant 8,769,204 - Delgross , et al. July 1, 2
2014-07-01
Method and apparatus for associating requests and responses with identification information
Grant 8,688,919 - O'Bleness , et al. April 1, 2
2014-04-01
Arithmetic logic and shifting device for use in a processor
Grant 8,688,761 - Ahmed , et al. April 1, 2
2014-04-01
Way-selecting translation lookaside buffer
Grant 8,631,206 - O'Bleness , et al. January 14, 2
2014-01-14
Implementing direct access caches in coherent multiprocessors
Grant 8,533,401 - Edirisooriya , et al. September 10, 2
2013-09-10
Programmable cache access protocol to optimize power consumption and performance
Grant 8,458,404 - Delgross , et al. June 4, 2
2013-06-04
Method and apparatus for data-less bus query
Grant 8,296,525 - O'Bleness , et al. October 23, 2
2012-10-23
Apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode
Grant 8,195,916 - Bassett , et al. June 5, 2
2012-06-05
Arithmetic Logic And Shifting Device For Use In A Processor
App 20120083912 - Ahmed; Muhammad ;   et al.
2012-04-05
Method and apparatus for hardware-configurable multi-policy coherence protocol
Grant 8,135,916 - O'Bleness , et al. March 13, 2
2012-03-13
Arithmetic logic and shifting device for use in a processor
Grant 8,099,448 - Ahmed , et al. January 17, 2
2012-01-17
Power optimized replay of blocked operations in a pipilined architecture
Grant 7,966,477 - Jamil , et al. June 21, 2
2011-06-21
Method and system for variable thread allocation and switching in a multithreaded processor
Grant 7,917,907 - Ahmed , et al. March 29, 2
2011-03-29
Controlling execution mode of program threads by applying a mask to a control register in a multi-threaded processor
Grant 7,849,466 - Codrescu , et al. December 7, 2
2010-12-07
Apparatus and Method to Translate Virtual Addresses to Physical Addresses in a Base Plus Offset Addressing Mode
App 20100228944 - Bassett; Paul Douglas ;   et al.
2010-09-09
Apparatus and method for arbitrating heterogeneous agents in on-chip busses
Grant 7,765,349 - Edirisooriya , et al. July 27, 2
2010-07-27
Method and apparatus for optimizing line writes in cache coherent systems
Grant 7,757,046 - Jamil , et al. July 13, 2
2010-07-13
Apparatus and method for power optimized replay via selective recirculation of instructions
Grant 7,725,683 - Jamil , et al. May 25, 2
2010-05-25
Method and apparatus for providing a low power mode for a processor while maintaining snoop throughput
Grant 7,694,080 - Merrell , et al. April 6, 2
2010-04-06
Cache memory to support a processor's power mode of operation
Grant 7,685,379 - Edirisooriya , et al. March 23, 2
2010-03-23
Method and apparatus for implementing heterogeneous interconnects
Grant 7,640,387 - Edirisooriya , et al. December 29, 2
2009-12-29
System and apparatus for early fixed latency subtractive decoding
Grant 7,634,603 - Edirisooriya , et al. December 15, 2
2009-12-15
Low power microprocessor cache memory and method of operation
Grant 7,620,778 - Mohammad , et al. November 17, 2
2009-11-17
Processor and method of grouping and executing dependent instructions in a packet
Grant 7,523,295 - Codrescu , et al. April 21, 2
2009-04-21
Cache memory to support a processor's power mode of operation
Grant 7,487,299 - Edirisooriya , et al. February 3, 2
2009-02-03
Method and apparatus for supporting opportunistic sharing in coherent multiprocessors
Grant 7,464,227 - Edirisooriya , et al. December 9, 2
2008-12-09
System and Apparatus for Early Fixed Latency Subtractive Decoding
App 20080282008 - Edirisooriya; Samantha J. ;   et al.
2008-11-13
Method And Apparatus For Implementing Heterogeneous Interconnects
App 20080250168 - Edirisooriya; Samantha J. ;   et al.
2008-10-09
Apparatus and method for arbitrating heterogeneous agents in on-chip busses
Grant 7,428,607 - Edirisooriya , et al. September 23, 2
2008-09-23
Method and apparatus for preventing and recovering from TLB corruption by soft error
Grant 7,415,633 - Jamil , et al. August 19, 2
2008-08-19
System and apparatus for early fixed latency subtractive decoding
Grant 7,406,553 - Edirisooriya , et al. July 29, 2
2008-07-29
Systems and methods for early fixed latency subtractive decoding including speculative acknowledging
Grant 7,406,552 - Edirisooriya , et al. July 29, 2
2008-07-29
Cache memory to support a processor's power mode of operation
Grant 7,404,043 - Edirisooriya , et al. July 22, 2
2008-07-22
Pushing of clean data to one or more processors in a system having a coherency protocol
Grant 7,366,845 - Jamil , et al. April 29, 2
2008-04-29
Method and apparatus for implementing heterogeneous interconnects
Grant 7,353,317 - Edirisooriya , et al. April 1, 2
2008-04-01
Cache memory to support a processor's power mode of operation
Grant 7,290,093 - Edirisooriya , et al. October 30, 2
2007-10-30
System And Apparatus For Early Fixed Latency Subtractive Decoding
App 20070186019 - Edirisooriya; Samantha J. ;   et al.
2007-08-09
Method and apparatus for fixed latency subtractive decoding
App 20070162672 - Edirisooriya; Samantha J. ;   et al.
2007-07-12
Power/performance optimized cache using memory write prevention through write snarfing
Grant 7,234,028 - Edirisooriya , et al. June 19, 2
2007-06-19
System and apparatus for early fixed latency subtractive decoding
Grant 7,219,176 - Edirisooriya , et al. May 15, 2
2007-05-15
Arithmethic logic and shifting device for use in a processor
App 20070100923 - Ahmed; Muhammad ;   et al.
2007-05-03
Pointer computation method and system for a scalable, programmable circular buffer
App 20070094478 - Plondke; Erich ;   et al.
2007-04-26
Mechanism handling race conditions in FRC-enabled processors
Grant 7,194,671 - Tu , et al. March 20, 2
2007-03-20
System and method of controlling multiple program threads within a multithreaded processor
App 20070016759 - Codrescu; Lucian ;   et al.
2007-01-18
Direct processor cache access within a system having a coherent multi-processor protocol
Grant 7,159,077 - Tu , et al. January 2, 2
2007-01-02
Apparatus and method for supporting heterogeneous agents in on-chip busses
App 20060271716 - Edirisooriya; Samantha J. ;   et al.
2006-11-30
Low power microprocessor cache memory and method of operation
App 20060268592 - Mohammad; Baker ;   et al.
2006-11-30
Apparatus and method for granting concurrent ownership to support heterogeneous agents in on-chip busses having different grant-to-valid latencies
Grant 7,143,220 - Edirisooriya , et al. November 28, 2
2006-11-28
Transfer of cache lines on-chip between processing cores in a multi-core system
Grant 7,120,755 - Jamil , et al. October 10, 2
2006-10-10
Method and system for variable thread allocation and switching in a multithreaded processor
App 20060218559 - Ahmed; Muhammad ;   et al.
2006-09-28
Processor and method of grouping and executing dependent instructions in a packet
App 20060212681 - Codrescu; Lucian ;   et al.
2006-09-21
Variable interleaved multithreaded processor method and system
App 20060206902 - Jamil; Sujat ;   et al.
2006-09-14
Methods and apparatus for cache intervention
Grant 7,100,001 - Edirisooriya , et al. August 29, 2
2006-08-29
Dirty line hint array for cache flushing
App 20060143397 - O'Bleness; R. Frank ;   et al.
2006-06-29
Method and apparatus for providing a low power mode for a processor while maintaining snoop throughput
App 20060143409 - Merrell; Quinn W. ;   et al.
2006-06-29
Method and apparatus for implementing heterogeneous interconnects
App 20060143358 - Edirisooriya; Samantha J. ;   et al.
2006-06-29
Methods and apparatus for cache intervention
Grant 7,062,613 - Jamil , et al. June 13, 2
2006-06-13
On-die mechanism for high-reliability processor
Grant 7,055,060 - Nguyen , et al. May 30, 2
2006-05-30
Techniques for pushing data to a processor cache
App 20060112238 - Jamil; Sujat ;   et al.
2006-05-25
Method and apparatus for scalable disambiguated coherence in shared storage hierarchies
Grant 7,003,632 - Jamil , et al. February 21, 2
2006-02-21
Direct processor cache access within a system having a coherent multi-processor protocol
App 20060004965 - Tu; Steven J. ;   et al.
2006-01-05
Direct processor cache access within a system having a coherent multi-processor protocol
App 20060004961 - Tu; Steven J. ;   et al.
2006-01-05
Methods and apparatus for cache intervention
Grant 6,983,348 - Jamil , et al. January 3, 2
2006-01-03
Pushing of clean data to one or more processors in a system having a coherency protocol
App 20050289303 - Jamil, Sujat ;   et al.
2005-12-29
Apparatus and method for supporting heterogeneous agents in on-chip busses
App 20050216632 - Edirisooriya, Samantha J. ;   et al.
2005-09-29
Cache memory to support a processor's power mode of operation
App 20050204195 - Edirisooriya, Samantha J. ;   et al.
2005-09-15
Cache memory to support a processor's power mode of operation
App 20050204202 - Edirisooriya, Samantha J. ;   et al.
2005-09-15
Cache memory to support a processor's power mode of operation
App 20050193176 - Edirisooriya, Samantha J. ;   et al.
2005-09-01
Methods and apparatus for cache intervention
App 20050166020 - Jamil, Sujat ;   et al.
2005-07-28
Methods and apparatus to dispatch interrupts in multi-processor systems
App 20050125582 - Tu, Steven J. ;   et al.
2005-06-09
Apparatus and method for power optimized replay
App 20050071603 - Jamil, Sujat ;   et al.
2005-03-31
Method and apparatus for preventing and recovering from TLB corruption by soft error
App 20040193992 - Jamil, Sujat ;   et al.
2004-09-30
Methods and apparatus for transferring cache block ownership
Grant 6,775,748 - Jamil , et al. August 10, 2
2004-08-10
Methods and apparatus for detecting an address conflict
App 20040153611 - Jamil, Sujat ;   et al.
2004-08-05
Cache memory to support a processor's power mode of operation
App 20040133746 - Edirisooriya, Samantha J. ;   et al.
2004-07-08
Implementing direct access caches in coherent multiprocessors
App 20040128450 - Edirisooriya, Samantha J. ;   et al.
2004-07-01
Power/performance optimized caches using memory write prevention through write snarfing
App 20040128451 - Edirisooriya, Samantha J. ;   et al.
2004-07-01
On-die mechanism for high-reliability processor
App 20040123201 - Nguyen, Hang T. ;   et al.
2004-06-24
Method and apparatus for cache coherency between heterogeneous agents and limiting data transfers among symmetric processors
App 20040111563 - Edirisooriya, Samantha J. ;   et al.
2004-06-10
Method and apparatus for supporting opportunistic sharing in coherent multiprocessors
App 20040111566 - Edirisooriya, Samantha J. ;   et al.
2004-06-10
Method and apparatus for preventing and recovering from TLB corruption by soft error
Grant 6,718,494 - Jamil , et al. April 6, 2
2004-04-06
Method and apparatus for optimizing line writes in cache coherent systems
App 20040064643 - Jamil, Sujat ;   et al.
2004-04-01
Method and apparatus for fixed latency subtractive decoding
App 20040064616 - Edirisooriya, Samantha J. ;   et al.
2004-04-01
Method, system, and apparatus for an efficient cache to support multiple configurations
App 20040015669 - Edirisooriya, Samantha J. ;   et al.
2004-01-22
Method and apparatus for scalable disambiguated coherence in shared storage hierarchies
App 20030233523 - Jamil, Sujat ;   et al.
2003-12-18
System and method for silent data corruption prevention due to next instruction pointer corruption by soft errors
Grant 6,658,621 - Jamil , et al. December 2, 2
2003-12-02
Method and apparatus for scalable disambiguated coherence in shared storage hierarchies
Grant 6,651,145 - Jamil , et al. November 18, 2
2003-11-18
Conditional read and invalidate for use in coherent multiprocessor systems
App 20030195939 - Edirisooriya, Samatha J. ;   et al.
2003-10-16
Methods and apparatus for cache intervention
App 20030154352 - Jamil, Sujat ;   et al.
2003-08-14
Methods and apparatus for cache intervention
App 20030154350 - Edirisooriya, Samantha J. ;   et al.
2003-08-14
Methods and apparatus for transferring cache block ownership
App 20030140200 - Jamil, Sujat ;   et al.
2003-07-24
Transfer of cache lines on-chip between processing cores in a multi-core system
App 20030126365 - Jamil, Sujat ;   et al.
2003-07-03
Mechanism handling race conditions in FRC-enabled processors
App 20030126142 - Tu, Steven J. ;   et al.
2003-07-03
Validating prediction for branches in a cluster via comparison of predicted and condition selected tentative target addresses and validation of branch conditions
Grant 6,304,960 - Yeh , et al. October 16, 2
2001-10-16
System for processing a cluster of instructions where the instructions are issued to the execution units having a priority order according to a template associated with the cluster of instructions
Grant 6,240,510 - Yeh , et al. May 29, 2
2001-05-29

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