JAMES-ROXBY; Philip B.

Patent Applications and Registrations

Patent applications and USPTO patent grants for JAMES-ROXBY; Philip B..The latest application filed is for "control and reconfiguration of data flow graphs on heterogeneous computing platform".

Company Profile

7.48.9

JAMES-ROXBY; Philip B. - Longmont CO

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Control And Reconfiguration Of Data Flow Graphs On Heterogeneous Computing Platform App 20220206766 - HSU; Chia-Jui ; et al.	2022-06-30
Control and reconfiguration of data flow graphs on heterogeneous computing platform Grant 11,281,440 - Hsu , et al. March 22, 2	2022-03-22
Dataflow Graph Programming Environment For A Heterogenous Processing System App 20220058005 - GUPTA; Shail Aditya ; et al.	2022-02-24
Converting floating point data into integer data using a dynamically adjusted scale factor Grant 11,216,275 - James-Roxby , et al. January 4, 2	2022-01-04
Dataflow graph programming environment for a heterogenous processing system Grant 11,204,745 - Gupta , et al. December 21, 2	2021-12-21
Streaming interconnect architecture for data processing engine array Grant 10,990,552 - Bilski , et al. April 27, 2	2021-04-27
Compilation flow for a heterogeneous multi-core architecture Grant 10,860,766 - Sivaraman , et al. December 8, 2	2020-12-08
Dataflow Graph Programming Environment For A Heterogenous Processing System App 20200371761 - Gupta; Shail Aditya ; et al.	2020-11-26
Compilation Flow For A Heterogeneous Multi-core Architecture App 20200372200 - Sivaraman; Mukund ; et al.	2020-11-26
Control and reconfiguration of data flow graphs on heterogeneous computing platform Grant 10,802,807 - Hsu , et al. October 13, 2	2020-10-13
Device with data processing engine array Grant 10,747,690 - Bilski , et al. A	2020-08-18
Device With Data Processing Engine Array App 20190303311 - Bilski; Goran HK ; et al.	2019-10-03
Heterogeneous multiprocessor platform targeting programmable integrated circuits Grant 9,846,660 - Styles , et al. December 19, 2	2017-12-19
Methods and circuits for debugging circuit designs Grant 9,678,150 - Schelle , et al. June 13, 2	2017-06-13
Methods And Circuits For Debugging Circuit Designs App 20170115348 - Schelle; Graham F. ; et al.	2017-04-27
Heterogeneous Multiprocessor Platform Targeting Programmable Integrated Circuits App 20160132441 - Styles; Henry E. ; et al.	2016-05-12
Heterogeneous multiprocessor program compilation targeting programmable integrated circuits Grant 9,218,443 - Styles , et al. December 22, 2	2015-12-22
Redundantly validating values with a processor and a check circuit Grant 8,595,442 - James-Roxby , et al. November 26, 2	2013-11-26
Transaction-level lockstep Grant 8,479,042 - James-Roxby , et al. July 2, 2	2013-07-02
Methods and systems with transaction-level lockstep Grant 8,443,230 - James-Roxby , et al. May 14, 2	2013-05-14
Method for scheduling a network packet processor Grant 8,284,772 - James-Roxby , et al. October 9, 2	2012-10-09
Communicating state data between stages of pipelined packet processor Grant 8,127,262 - James-Roxby , et al. February 28, 2	2012-02-28
Method and apparatus for initializing a system configured in a programmable logic device Grant 8,122,239 - James-Roxby , et al. February 21, 2	2012-02-21
Method for message processing on a programmable logic device Grant 8,065,130 - Brebner , et al. November 22, 2	2011-11-22
Generation of executable threads having source code specifications that describe network packets Grant 8,032,874 - Keller , et al. October 4, 2	2011-10-04
Pipeline for processing network packets Grant 7,990,867 - Keller , et al. August 2, 2	2011-08-02
Machines for inserting or removing fixed length data at a fixed location in a serial data stream Grant 7,949,790 - James-Roxby , et al. May 24, 2	2011-05-24
Method and apparatus for providing an interface between a programmable circuit and a processor Grant 7,949,793 - James-Roxby , et al. May 24, 2	2011-05-24
Thread circuits and a broadcast channel in programmable logic Grant 7,823,162 - Keller , et al. October 26, 2	2010-10-26
Method for simulating a processor of network packets Grant 7,792,117 - Keller , et al. September 7, 2	2010-09-07
Circuit for modification of a network packet by insertion or removal of a data segment Grant 7,788,402 - Keller , et al. August 31, 2	2010-08-31
Generation of a specification of a network packet processor Grant 7,784,014 - Brebner , et al. August 24, 2	2010-08-24
Method and apparatus for multithreading on a programmable logic device Grant 7,770,179 - James-Roxby , et al. August 3, 2	2010-08-03
Method and apparatus for configuring a processor embedded in an integrated circuit for use as a logic element Grant 7,698,449 - Keller , et al. April 13, 2	2010-04-13
Bootable integrated circuit device for readback encoding of configuration data Grant 7,689,726 - Sundararajan , et al. March 30, 2	2010-03-30
Memory arrangement for message processing by a plurality of threads Grant 7,653,895 - James-Roxby , et al. January 26, 2	2010-01-26
Integrated circuit having a routing element selectively operable to function as an antenna Grant 7,627,291 - James-Roxby , et al. December 1, 2	2009-12-01
Method and apparatus for application-specific programmable memory architecture and interconnection network on a chip Grant 7,574,680 - Kulkarni , et al. August 11, 2	2009-08-11
Method for message processing on a programmable logic device Grant 7,552,042 - Brebner , et al. June 23, 2	2009-06-23
Methods of implementing embedded processor systems including state machines Grant 7,552,405 - James-Roxby June 23, 2	2009-06-23
Bootable programmable logic device for internal decoding of encoded configuration data Grant 7,328,335 - Sundararajan , et al. February 5, 2	2008-02-05
Method and apparatus for a programmable interface of a soft platform on a programmable logic device Grant 7,228,520 - Keller , et al. June 5, 2	2007-06-05
Reconfiguration of a programmable logic device using internal control Grant 7,227,378 - Blodget , et al. June 5, 2	2007-06-05
Method and apparatus for application-specific programmable memory architecture and interconnection network on a chip Grant 7,185,309 - Kulkarni , et al. February 27, 2	2007-02-27
Integration of a run-time parameterizable core with a static circuit design Grant 7,139,995 - James-Roxby , et al. November 21, 2	2006-11-21
Method and apparatus for processing data stored in a memory shared among a plurality of processors Grant 7,133,978 - James-Roxby , et al. November 7, 2	2006-11-07
Using an embedded processor to implement a finite state machine Grant 7,131,077 - James-Roxby , et al. October 31, 2	2006-10-31
Method of and apparatus for enabling a hardware module to interact with a data structure Grant 7,076,596 - Keller , et al. July 11, 2	2006-07-11
Method of using a hardware library in a programmable logic device Grant 7,028,283 - Keller , et al. April 11, 2	2006-04-11
Reconfiguration of a programmable logic device using internal control App 20050193358 - Blodget, Brandon J. ; et al.	2005-09-01
Reconfiguration of a programmable logic device using internal control Grant 6,920,627 - Blodget , et al. July 19, 2	2005-07-19
Method and system for generating a circuit design including a peripheral component connected to a bus Grant 6,883,147 - Ballagh , et al. April 19, 2	2005-04-19
Reconfiguration of a programmable logic device using internal control App 20040117755 - Blodget, Brandon J. ; et al.	2004-06-17
Reconfigurable priority encoding Grant 6,621,295 - James-Roxby , et al. September 16, 2	2003-09-16

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