loadpatents
name:-0.0056140422821045
name:-0.073723077774048
name:-0.0010380744934082
James; David V. Patent Filings

James; David V.

Patent Applications and Registrations

Patent applications and USPTO patent grants for James; David V..The latest application filed is for "memory system having synchronous-link dram (sldram) devices and controller".

Company Profile
0.56.3
  • James; David V. - Palo Alto CA US
  • James; David V - Palo Alto CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Method for pacing multi-rate time sensitive traffic on Ethernet and bridge connected networks
Grant 8,619,567 - James December 31, 2
2013-12-31
Method and apparatus for configuring signal lines according to idle codes
Grant 8,073,005 - James , et al. December 6, 2
2011-12-06
Random access memory (RAM) method of operation and device for search engine systems
Grant 7,474,586 - James , et al. January 6, 2
2009-01-06
Content addressable memory (CAM) device having selectable access and method therefor
Grant 7,401,180 - James , et al. July 15, 2
2008-07-15
Random access memory (RAM) method of operation and device for search engine systems
Grant 7,379,352 - James , et al. May 27, 2
2008-05-27
Method of and apparatus for implementing and sending an asynchronous control mechanism packet used to control bridge devices within a network of IEEE Std 1394 serial buses
Grant 7,321,592 - Scheel , et al. January 22, 2
2008-01-22
Method and apparatus for configuring signal lines according to idle codes
Grant 7,301,961 - James , et al. November 27, 2
2007-11-27
Method and apparatus for framing a data packet
Grant 7,283,565 - James , et al. October 16, 2
2007-10-16
Apparatus and method for associating information values with portions of a content addressable memory (CAM) device
Grant 7,185,141 - James , et al. February 27, 2
2007-02-27
Method and apparatus for restricted search operation in content addressable memory (CAM) devices
Grant 7,117,300 - James , et al. October 3, 2
2006-10-03
Packet based communication for content addressable memory (CAM) devices and systems
Grant 7,117,301 - James , et al. October 3, 2
2006-10-03
AV/C commands for accessing a hard disk device
Grant 7,085,480 - James August 1, 2
2006-08-01
Device identification method for systems having multiple device branches
Grant 7,073,018 - James , et al. July 4, 2
2006-07-04
Method of and apparatus for directly mapping communications through a router between nodes on different buses within a network of buses
Grant 6,993,022 - James , et al. January 31, 2
2006-01-31
Search engine device and method for generating output search responses from multiple input search responses
Grant 6,954,823 - James , et al. October 11, 2
2005-10-11
System and method for efficiently performing scheduling operations in an electronic device
Grant 6,928,646 - James , et al. August 9, 2
2005-08-09
Maintaining communications in a bus bridge interconnect
Grant 6,910,090 - Scheel , et al. June 21, 2
2005-06-21
Data preclassifier method and apparatus for content addressable memory (CAM) device
Grant 6,906,936 - James , et al. June 14, 2
2005-06-14
Content addressable memory (CAM) device decoder circuit
Grant 6,903,951 - James , et al. June 7, 2
2005-06-07
Apparatus and method for inter-node communication
Grant 6,898,201 - James , et al. May 24, 2
2005-05-24
Method and apparatus for storing mask values in a content addressable memory (CAM) device
Grant 6,892,273 - James , et al. May 10, 2
2005-05-10
Random access memory (RAM) method of operation and device for search engine systems
Grant 6,879,523 - James , et al. April 12, 2
2005-04-12
Method and apparatus for identifying content addressable memory device results for multiple requesting sources
Grant 6,876,558 - James , et al. April 5, 2
2005-04-05
System and method for utilizing a memory device to support isochronous processes
Grant 6,847,650 - Stone , et al. January 25, 2
2005-01-25
Result compare circuit and method for content addressable memory (CAM) device
Grant 6,845,024 - Wanzakhade , et al. January 18, 2
2005-01-18
Method and system for quarantine during bus topology configuration
Grant 6,810,452 - James , et al. October 26, 2
2004-10-26
Cascadable content addressable memory (CAM) device and architecture
Grant 6,763,426 - James , et al. July 13, 2
2004-07-13
System for and method of efficiently controlling memory accesses in a multiprocessor computer system
Grant RE38,514 - James , et al. May 11, 2
2004-05-11
Method and system for supporting multiprocessor TLB-purge instructions using directed write transactions
Grant 6,684,315 - James , et al. January 27, 2
2004-01-27
Method and system for using a new bus identifier resulting from a bus topology change
Grant 6,647,446 - James , et al. November 11, 2
2003-11-11
Memory system having synchronous-link DRAM (SLDRAM) devices and controller
App 20030126356 - Gustavson, David B. ;   et al.
2003-07-03
System and method to effectively compensate for delays in an electronic interconnect
Grant 6,557,067 - James , et al. April 29, 2
2003-04-29
Method and system for adjusting isochronous bandwidths on a bus
Grant 6,539,450 - James , et al. March 25, 2
2003-03-25
System and method for updating from a read-only to a read-write entry and concurrently invalidating stale cache copies from head-to-tail and tail-to-head directions
Grant 6,496,907 - James December 17, 2
2002-12-17
Method of and apparatus for implementing and sending an asynchronous control mechanism packet used to control bridge devices within a network of IEEE Std 1394 serial buses
App 20020167953 - Scheel, Richard K. ;   et al.
2002-11-14
Method of and apparatus for implementing and sending an asynchronous control mechanism packet used to control bridge devices within a network of IEEE STD 1394 serial buses
Grant 6,445,711 - Scheel , et al. September 3, 2
2002-09-03
Memory system having synchronous-link DRAM (SLDRAM) devices and controller
Grant 6,442,644 - Gustavson , et al. August 27, 2
2002-08-27
Method and system for supporting multiprocessor TLB-purge instructions using directed write transactions
App 20020069329 - James, David V. ;   et al.
2002-06-06
Bifurcated data and command/address communication bus architecture for random access memories employing synchronous communication protocols
Grant 6,226,723 - Gustavson , et al. May 1, 2
2001-05-01
Time multiplexing of cyclic redundancy functions in point-to-point ringlet-based computer systems
Grant 6,208,645 - James , et al. March 27, 2
2001-03-27
Descriptor mechanism for assuring indivisible execution of AV/C operations
Grant 6,133,938 - James October 17, 2
2000-10-17
System and method for changing the states of directory-based caches and memories from read/write to read-only
Grant 6,035,376 - James March 7, 2
2000-03-07
System for transferring data specified in a transaction request as a plurality of move transactions responsive to receipt of a target availability signal
Grant 6,006,289 - James , et al. December 21, 1
1999-12-21
Efficient arbitration within point-to-point ringlet-based computer systems
Grant 5,898,876 - James April 27, 1
1999-04-27
System for an method of efficiently controlling memory accesses in a multiprocessor computer system
Grant 5,895,496 - James , et al. April 20, 1
1999-04-20
System for generating and sending a critical-world-first data response packet by creating response packet having data ordered in the order best matching the desired order
Grant 5,845,145 - James , et al. December 1, 1
1998-12-01
System and method for efficiently routing data packets in a computer interconnect
Grant 5,841,989 - James , et al. November 24, 1
1998-11-24
System and method for preventing stale data in multiple processor computer systems
Grant 5,829,035 - James , et al. October 27, 1
1998-10-27
Method and apparatus for using condition codes to nullify instructions based on results of previously-executed instructions on a computer processor
Grant 5,815,695 - James , et al. September 29, 1
1998-09-29
DMA controller with mechanism for conditional action under control of status register, prespecified parameters, and condition field of channel command
Grant 5,717,952 - Christiansen , et al. February 10, 1
1998-02-10
Processor with sequences of processor instructions for locked memory updates
Grant 5,574,922 - James November 12, 1
1996-11-12
System for finding and setting address portion of variable-length character string by XOR-ing portion in number of bytes within single instruction
Grant 5,495,592 - James , et al. February 27, 1
1996-02-27
Elasticity buffer for data/clock synchronization
Grant 5,323,426 - James , et al. June 21, 1
1994-06-21
Self-correcting synchronization signal method and apparatus
Grant 5,052,029 - James , et al. September 24, 1
1991-09-24
Interrupt system using masking register in processor for selectively establishing device eligibility to interrupt a particular processor
Grant 4,779,195 - James October 18, 1
1988-10-18
Direct input/output in a virtual memory system
Grant 4,777,589 - Boettner , et al. October 11, 1
1988-10-11
Hybrid hardware/software method and apparatus for virtual memory address translation using primary and secondary translation buffers
Grant 4,774,653 - James September 27, 1
1988-09-27
Method and apparatus for performing variable length data read transactions
Grant 4,703,418 - James October 27, 1
1987-10-27

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