Jallice; Derwin L.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Jallice; Derwin L..The latest application filed is for "enhanced single event upset immune latch circuit".
- Jallice; Derwin L. - Austin TX
- Jallice; Derwin L. - Reston VA
| Patent | Date |
|---|---|
| Enhanced single event upset immune latch circuit Grant 6,275,080 - Phan , et al. August 14, 2 | 2001-08-14 |
| Extended segmented precharge architecture Grant 5,592,426 - Jallice , et al. January 7, 1 | 1997-01-07 |
| CMOS off chip driver for fault tolerant cold sparing Grant 5,117,129 - Hoffman , et al. May 26, 1 | 1992-05-26 |
| Zero standby power, radiation hardened, memory redundancy circuit Grant 4,996,670 - Ciraula , et al. February 26, 1 | 1991-02-26 |
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