Jain; Paras Mal

Patent Applications and Registrations

Patent applications and USPTO patent grants for Jain; Paras Mal.The latest application filed is for "reset domain crossing detection and simulation".

Company Profile

2.10.12

Jain; Paras Mal - Cupertino CA
JAIN; Paras Mal - Mountain View CA
Jain; Paras Mal - Greater Noida IN
Jain; Paras Mal - Fremont CA
Jain; Paras Mal - Rajasthan IN
JAIN; Paras Mal - Alwar IN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Convergence centric coverage for clock domain crossing (CDC) jitter in simulation Grant 11,403,450 - Malani , et al. August 2, 2	2022-08-02
Determining and verifying metastability in clock domain crossings Grant 11,347,917 - Ahuja , et al. May 31, 2	2022-05-31
Reset Domain Crossing Detection And Simulation App 20220092244 - RAHIM; Fahim ; et al.	2022-03-24
Determining And Verifying Metastability In Clock Domain Crossings App 20210350053 - AHUJA; Deepak ; et al.	2021-11-11
Clock domain crossing verification of integrated circuit design using parameter inference Grant 11,087,059 - Malani , et al. August 10, 2	2021-08-10
Convergence Centric Coverage For Clock Domain Crossing (cdc) Jitter In Simulation App 20210209279 - MALANI; Anshu ; et al.	2021-07-08
Hierarchical Abstraction Flow Using Parameter Inference App 20200401749 - MALANI; Anshu ; et al.	2020-12-24
System and method for managing and composing verification engines Grant 10,387,605 - Mneimneh , et al. A	2019-08-20
System and method to facilitate stateless serving gateway operations in a network environment Grant 10,356,830 - Jain , et al. July 16, 2	2019-07-16
System And Method To Facilitate Stateless Serving Gateway Operations In A Network Environment App 20180206275 - Jain; Paras Mal ; et al.	2018-07-19
System And Method For Managing And Composing Verification Engines App 20170024508 - Mneimneh; Maher ; et al.	2017-01-26
System and method for metastability verification of circuits of an integrated circuit Grant 8,856,706 - Mneimneh , et al. October 7, 2	2014-10-07
System And Method For Filtration Of Error Reports Respective Of Static And Quasi-static Signals Within An Integrated Circuit Design App 20140282322 - Sarwary; Mohamed Shaker ; et al.	2014-09-18
Hierarchical bottom-up clock domain crossing verification Grant 8,607,173 - Sarwary , et al. December 10, 2	2013-12-10
System And Method For Metastability Verification Of Circuits Of An Integrated Circuit App 20130246989 - MNEIMNEH; Maher ; et al.	2013-09-19
Hierarchical Bottom-up Clock Domain Crossing Verification App 20130239080 - SARWARY; Mohamed Shaker ; et al.	2013-09-12
System and method for metastability verification of circuits of an integrated circuit Grant 8,448,111 - Mneimneh , et al. May 21, 2	2013-05-21
System And Method For Metastability Verification Of Circuits Of An Integrated Circuit App 20120180015 - MNEIMNEH; Maher ; et al.	2012-07-12
Method For Recognizing And Verifying Fifo Structures In Integrated Circuit Designs App 20080008021 - SARWARY; Shaker ; et al.	2008-01-10

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