Jain; Dhruv
Patent Applications and Registrations
Patent applications and USPTO patent grants for Jain; Dhruv.The latest application filed is for "automated overclocking using a prediction model".
- Jain; Dhruv - Palo Alto CA
- Jain; Dhruv - Mississauga CA
- Jain; Dhruv - Woodland Hills CA
Trademarks
| Patent | Date |
|---|---|
| Increasing CPU clock speed to improve system performance Grant 11,379,337 - Partiwala , et al. July 5, 2 | 2022-07-05 |
| Automated Overclocking Using A Prediction Model App 20210405112 - Partiwala; Suketu ; et al. | 2021-12-30 |
| Interfaces Presentations On Displays App 20210397339 - Zhang; Ron Yiran ; et al. | 2021-12-23 |
| Interfaces Moves App 20210397399 - Zhang; Ron Yirang ; et al. | 2021-12-23 |
| Increasing Cpu Clock Speed To Improve System Performance App 20210326232 - Partiwala; Suketu ; et al. | 2021-10-21 |
| Output buffer with switchable output impedance Grant 7,479,799 - Raghavan , et al. January 20, 2 | 2009-01-20 |
| Master-slave flip-flop and clocking scheme Grant 7,408,393 - Jain , et al. August 5, 2 | 2008-08-05 |
| Output buffer to drive AC-coupled terminated transmission lines App 20070247194 - Jain; Dhruv | 2007-10-25 |
| Output buffer with switchable output impedance App 20070216445 - Raghavan; Gopal ; et al. | 2007-09-20 |
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