Jahinuzzaman; Shah M.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Jahinuzzaman; Shah M..The latest application filed is for "latch with redundancy and circuitry to protect against a soft error".
- Jahinuzzaman; Shah M. - Portland OR
- Jahinuzzaman; Shah M - Waterloo CA
- Jahinuzzaman; Shah M. - Waterloo CA
| Patent | Date |
|---|---|
| Latch with redundancy and circuitry to protect against a soft error Grant 10,848,134 - Gill , et al. November 24, 2 | 2020-11-24 |
| Latch With Redundancy And Circuitry To Protect Against A Soft Error App 20170093380 - GILL; BALKARAN ; et al. | 2017-03-30 |
| Soft error robust static random access memory cell storage configuration. Grant 7,872,938 - Sachdev , et al. January 18, 2 | 2011-01-18 |
| Soft error robust flip-flops Grant 7,714,628 - Sachdev , et al. May 11, 2 | 2010-05-11 |
| Soft Error Robust Static Random Access Memory Cell Storage Configuration App 20090316505 - Sachdev; Manoj ; et al. | 2009-12-24 |
| Soft error robust static random access memory cells Grant 7,613,067 - Sachdev , et al. November 3, 2 | 2009-11-03 |
| Soft Error Robust Flip-Flops App 20080180153 - Sachdev; Manoj ; et al. | 2008-07-31 |
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