loadpatents
name:-0.016482830047607
name:-0.01459813117981
name:-0.0036060810089111
Jaeger; Daniel J. Patent Filings

Jaeger; Daniel J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Jaeger; Daniel J..The latest application filed is for "forming interconnect without gate cut isolation blocking opening formation".

Company Profile
2.16.18
  • Jaeger; Daniel J. - Saratoga Springs NY
  • Jaeger; Daniel J. - Wappingers Falls NY
  • Jaeger; Daniel J - Wappingers Falls NY
  • Jaeger; Daniel J. - Hopewell Junction NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Forming interconnect without gate cut isolation blocking opening formation
Grant 11,056,398 - Jaeger , et al. July 6, 2
2021-07-06
Forming Interconnect Without Gate Cut Isolation Blocking Opening Formation
App 20210028067 - Jaeger; Daniel J. ;   et al.
2021-01-28
Method of forming semiconductor material in trenches having different widths, and related structures
Grant 10,714,376 - Chang , et al.
2020-07-14
Method Of Forming Semiconductor Material In Trenches Having Different Widths, And Related Structures
App 20190393077 - Chang; Chih-Chiang ;   et al.
2019-12-26
Partial sacrificial dummy gate with CMOS device with high-k metal gate
Grant 9,853,116 - Guo , et al. December 26, 2
2017-12-26
Partial Sacrificial Dummy Gate With Cmos Device With High-k Metal Gate
App 20160099332 - Guo; Dechao ;   et al.
2016-04-07
Partial sacrificial dummy gate with CMOS device with high-k metal gate
Grant 9,299,795 - Guo , et al. March 29, 2
2016-03-29
Partial Sacrificial Dummy Gate With Cmos Device With High-k Metal Gate
App 20150187897 - Guo; Dechao ;   et al.
2015-07-02
Partial sacrificial dummy gate with CMOS device with high-k metal gate
Grant 9,041,076 - Guo , et al. May 26, 2
2015-05-26
Semiconductor fin on local oxide
Grant 9,035,430 - Vega , et al. May 19, 2
2015-05-19
Semiconductor Fin On Local Oxide
App 20150044843 - Aquilino; Michael V. ;   et al.
2015-02-12
Sealed shallow trench isolation region
Grant 8,859,388 - Aquilino , et al. October 14, 2
2014-10-14
Partial Sacrificial Dummy Gate With Cmos Device With High-k Metal Gate
App 20140217481 - Guo; Dechao ;   et al.
2014-08-07
Metal oxide semiconductor field effect transistor (MOSFET) gate termination
Grant 8,704,332 - Baiocco , et al. April 22, 2
2014-04-22
Semiconductor Fin On Local Oxide
App 20140061862 - VEGA; Reinaldo A. ;   et al.
2014-03-06
Sealed Shallow Trench Isolation Region
App 20140015092 - Aquilino; Michael V. ;   et al.
2014-01-16
Metal oxide semiconductor field effect transistor (MOSFET) gate termination
Grant 8,629,028 - Baiocco , et al. January 14, 2
2014-01-14
Metal Oxide Semiconductor Field Effect Transistor (mosfet) Gate Termination
App 20130334618 - Baiocco; Christopher V. ;   et al.
2013-12-19
Metal Oxide Semiconductor Field Effect Transistor (mosfet) Gate Termination
App 20130337624 - Baiocco; Christopher V. ;   et al.
2013-12-19
Bipolar transistor integrated with metal gate CMOS devices
Grant 8,569,840 - Wallner , et al. October 29, 2
2013-10-29
Structure And Method For Reduction Of Vt-w Effect In High-k Metal Gate Devices
App 20130140670 - Aquilino; Michael V. ;   et al.
2013-06-06
Structure And Method For Reduction Of Vt-w Effect In High-k Metal Gate Devices
App 20120187522 - Aquilino; Michael V. ;   et al.
2012-07-26
Bipolar Transistor Integrated With Metal Gate Cmos Devices
App 20120139056 - Wallner; Thomas A. ;   et al.
2012-06-07
Method of forming bipolar transistor integrated with metal gate CMOS devices
Grant 8,129,234 - Wallner , et al. March 6, 2
2012-03-06
CMOS SiGe channel pFET and Si channel nFET devices with minimal STI recess
Grant 8,053,301 - Jaeger , et al. November 8, 2
2011-11-08
Bipolar Transistor Integrated With Metal Gate Cmos Devices
App 20110057266 - Wallner; Thomas A. ;   et al.
2011-03-10
Cmos Sige Channel Pfet And Si Channel Nfet Devices With Minimal Sti Recess
App 20100244198 - Jaeger; Daniel J. ;   et al.
2010-09-30

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed