loadpatents
name:-0.019912004470825
name:-0.018718957901001
name:-0.0016739368438721
Jacunski; Mark D. Patent Filings

Jacunski; Mark D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Jacunski; Mark D..The latest application filed is for "on-chip reliability monitor and method".

Company Profile
1.15.17
  • Jacunski; Mark D. - Colchester VT
  • Jacunski; Mark D - Colchester VT
  • Jacunski; Mark D. - Winnoski VT
  • Jacunski; Mark D. - Winooski VT
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Latching current sensing amplifier for memory array
Grant 10,535,379 - Anand , et al. Ja
2020-01-14
On-chip reliability monitor and method
Grant 10,429,434 - Fifield , et al. October 1, 2
2019-10-01
On-chip Reliability Monitor And Method
App 20190265293 - Fifield; John A. ;   et al.
2019-08-29
Static random access memory (SRAM) write assist circuit with improved boost
Grant 10,020,047 - Hunt-Schroeder , et al. July 10, 2
2018-07-10
Latching Current Sensing Amplifier For Memory Array
App 20170365302 - ANAND; Darren L. ;   et al.
2017-12-21
Latching current sensing amplifier for memory array
Grant 9,779,783 - Anand , et al. October 3, 2
2017-10-03
Static Random Access Memory (sram) Write Assist Circuit With Improved Boost
App 20170270999 - HUNT-SCHROEDER; Eric D. ;   et al.
2017-09-21
Latching Current Sensing Amplifier For Memory Array
App 20160372164 - ANAND; Darren L. ;   et al.
2016-12-22
Signal margin centering for single-ended eDRAM sense amplifier
Grant 9,093,175 - Barth, Jr. , et al. July 28, 2
2015-07-28
Memory array with on and off-state wordline voltages having different temperature coefficients
Grant 8,902,679 - Fifield , et al. December 2, 2
2014-12-02
SIGNAL MARGIN CENTERING FOR SINGLE-ENDED eDRAM SENSE AMPLIFIER
App 20140293715 - BARTH, JR.; JOHN E. ;   et al.
2014-10-02
Multi-bank random access memory structure with global and local signal buffering for improved performance
Grant 8,649,239 - Anand , et al. February 11, 2
2014-02-11
Memory Array With On And Off-state Wordline Voltages Having Different Temperature Coefficients
App 20140003164 - Fifield; John A. ;   et al.
2014-01-02
Multi-bank Random Access Memory Structure With Global And Local Signal Buffering For Improved Performance
App 20130315022 - Anand; Darren L. ;   et al.
2013-11-28
Morphing Memory Architecture
App 20120036315 - Reohr; William R. ;   et al.
2012-02-09
Timer lockout circuit for synchronous applications
Grant 7,221,601 - Jacunski , et al. May 22, 2
2007-05-22
Command multiplier for built-in-self-test
Grant 7,194,670 - Fales , et al. March 20, 2
2007-03-20
Method and structure for enabling a redundancy allocation during a multi-bank operation
Grant 7,085,180 - Fredeman , et al. August 1, 2
2006-08-01
Timer lockout circuit for synchronous applications
App 20060152994 - Jacunski; Mark D. ;   et al.
2006-07-13
Timer lockout circuit for synchronous applications
Grant 7,068,564 - Jacunski , et al. June 27, 2
2006-06-27
A Command Multiplier for Built-In-Self-Test
App 20050193253 - Fales, Jonathan R. ;   et al.
2005-09-01
Method and structure for enabling a redundancy allocation during a multi-bank operation
App 20050180230 - Fredeman, Gregory J. ;   et al.
2005-08-18
Timer lockout circuit for synchronous applications
App 20040264289 - Jacunski, Mark D ;   et al.
2004-12-30
Pre-charge circuit and method for memory devices with shared sense amplifiers
App 20030043666 - Jacunski, Mark D. ;   et al.
2003-03-06
DRAM word line voltage control to insure full cell writeback level
App 20020159301 - Ellis, Wayne F. ;   et al.
2002-10-31
Isolated well ESD device
Grant 6,399,990 - Brennan , et al. June 4, 2
2002-06-04
Programmable delay element and synchronous DRAM using the same
Grant 6,400,202 - Fifield , et al. June 4, 2
2002-06-04
Programmable delay element and synchronous dram using the same
App 20020030524 - Fifield, John A. ;   et al.
2002-03-14

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