Jacobs; Jarvis B.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Jacobs; Jarvis B..The latest application filed is for "method for manufacturing a semiconductor device using a nitrogen containing oxide layer".

Company Profile

0.7.8

Jacobs; Jarvis B. - Murphy TX US
Jacobs; Jarvis B. - Richardson TX
Jacobs; Jarvis B. - Dallas TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method for manufacturing a semiconductor device using a nitrogen containing oxide layer Grant 8,802,577 - Niimi , et al. August 12, 2	2014-08-12
Method For Manufacturing A Semiconductor Device Using A Nitrogen Containing Oxide Layer App 20120028431 - Niimi; Hiroaki ; et al.	2012-02-02
Method for manufacturing a semiconductor device having improved across chip implant uniformity Grant 7,569,464 - Kirmse , et al. August 4, 2	2009-08-04
Method for forming a mixed voltage circuit having complementary devices Grant 7,560,779 - Rodder , et al. July 14, 2	2009-07-14
Method For Manufacturing A Semiconductor Device Having Improved Across Chip Implant Uniformity App 20080153273 - Kirmse; Karen H.R. ; et al.	2008-06-26
Method for manufacturing a semiconductor device using a nitrogen containing oxide layer App 20070196970 - Niimi; Hiroaki ; et al.	2007-08-23
Semiconductor process using delay-compensated exposure Grant 6,866,974 - Kim , et al. March 15, 2	2005-03-15
Method of photolithographically forming extremely narrow transistor gate elements Grant 6,762,130 - Laaksonen , et al. July 13, 2	2004-07-13
Semiconductor process using delay-compensated exposure App 20040076896 - Kim, Keeho ; et al.	2004-04-22
Method of photolithographically forming extremely narrow transistor gate elements App 20030224606 - Laaksonen, Reima Tapani ; et al.	2003-12-04
Method for forming a mixed voltage circuit having complementary devices App 20030199133 - Rodder, Mark S. ; et al.	2003-10-23
Cost effective split-gate process that can independently optimize the low voltage(LV) and high voltage (HV) transistors to minimize reverse short channel effects App 20020052083 - Zhang, Xin ; et al.	2002-05-02
Low cost solution to integrate two different mosfet designs on a chip App 20010046740 - Kim, Youngmin ; et al.	2001-11-29
Semiconductor on silicon (SOI) transistor with a halo implant Grant 5,936,278 - Hu , et al. August 10, 1	1999-08-10

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