loadpatents
name:-0.009009838104248
name:-0.0073831081390381
name:-0.0031249523162842
Jack; Nathan D. Patent Filings

Jack; Nathan D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Jack; Nathan D..The latest application filed is for "semiconductor diodes employing back-side seimconductor or metal".

Company Profile
2.6.8
  • Jack; Nathan D. - Forest Grove OR
  • Jack; Nathan D. - Hillsboro OR
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Semiconductor diodes employing back-side semiconductor or metal
Grant 11,264,405 - Morrow , et al. March 1, 2
2022-03-01
Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers
Grant 10,756,078 - Di Sarro , et al. A
2020-08-25
Semiconductor Diodes Employing Back-side Seimconductor Or Metal
App 20190096917 - Morrow; Patrick ;   et al.
2019-03-28
Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers
Grant 10,181,463 - Di Sarro , et al. Ja
2019-01-15
Structure And Method For Dynamic Biasing To Improve Esd Robustness Of Current Mode Logic (cml) Drivers
App 20170133839 - Di Sarro; James P. ;   et al.
2017-05-11
Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers
Grant 9,620,497 - Di Sarro , et al. April 11, 2
2017-04-11
Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers
Grant 9,219,055 - Di Sarro , et al. December 22, 2
2015-12-22
Structure And Method For Dynamic Biasing To Improve Esd Robustness Of Current Mode Logic (cml) Drivers
App 20150363539 - Di Sarro; James P. ;   et al.
2015-12-17
Structure And Method For Dynamic Biasing To Improve Esd Robustness Of Current Mode Logic (cml) Drivers
App 20150364914 - Di Sarro; James P. ;   et al.
2015-12-17
Inverter-embedded Silicon Controlled Rectifier
App 20150124360 - Jack; Nathan D. ;   et al.
2015-05-07
Structure And Method For Dynamic Biasing To Improve Esd Robustness Of Current Mode Logic (cml) Drivers
App 20130335099 - Di Sarro; James P. ;   et al.
2013-12-19

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