Iyer; Mahesh A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Iyer; Mahesh A..The latest application filed is for "temperature control systems and methods for integrated circuits".

Company Profile

23.73.67

Iyer; Mahesh A. - Fremont CA
Iyer; Mahesh A. - Freemont CA
Iyer; Mahesh A. - Portland OR
Iyer; Mahesh A. - Sunnyvale CA
Iyer; Mahesh A. - Cranbury NJ

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Temperature Control Systems And Methods For Integrated Circuits App 20220215147 - Lim; Teik Wah ; et al.	2022-07-07
Methods for handling integrated circuit dies with defects Grant 11,368,158 - Subbareddy , et al. June 21, 2	2022-06-21
Systems And Methods To Reduce Voltage Guardband App 20220113694 - Kumashikar; Mahesh K. ; et al.	2022-04-14
Controlled Transition Between Configuration Mode and User Mode to Reduce Current-Resistance Voltage Drop App 20220113756 - Maheshwari; Atul ; et al.	2022-04-14
Power Allocation using Multiple Voltage Domains for Programmable Logic Devices App 20220116045 - Kumashikar; Mahesh K. ; et al.	2022-04-14
Adjustable Integrated Circuit Operation Using Power Headroom App 20220113788 - Kumashikar; Mahesh K. ; et al.	2022-04-14
Power Management using Voltage Islands on Programmable Logic Devices App 20220116041 - Kumashikar; Mahesh K. ; et al.	2022-04-14
Switch Based On Load Current App 20220115959 - Hossain; MD Altaf ; et al.	2022-04-14
Dynamic Loadlines For Programmable Fabric Devices App 20220114316 - Li; Yuet ; et al.	2022-04-14
Circuits And Methods For Accessing Signals In Integrated Circuits App 20220077856 - Peng; Yi ; et al.	2022-03-10
Systems And Methods For Circuit Design Dependent Programmable Maximum Junction Temperatures App 20220004688 - Srinivasan; Archanna ; et al.	2022-01-06
Methods And Apparatus For Reducing Reliability Degradation On An Integrated Circuit App 20210383049 - Cheng; Ning ; et al.	2021-12-09
Fast Memory For Programmable Devices App 20210384912 - Weber; Scott Jeremy ; et al.	2021-12-09
Methods and apparatus for reducing reliability degradation on an integrated circuit Grant 11,113,442 - Cheng , et al. September 7, 2	2021-09-07
Fast memory for programmable devices Grant 11,101,804 - Weber , et al. August 24, 2	2021-08-24
Techniques For Providing Optimizations Based On Categories Of Slack In Timing Paths App 20210216692 - Whitty; Scott ; et al.	2021-07-15
Methods and apparatus to insert buffers in a dataflow graph Grant 10,965,536 - ChoFleming, Jr. , et al. March 30, 2	2021-03-30
Methods for incremental circuit physical synthesis Grant 10,936,772 - Iyer , et al. March 2, 2	2021-03-02
Method and apparatus for performing rewind structural verification of retimed circuits driven by a plurality of clocks Grant 10,922,461 - Iyer , et al. February 16, 2	2021-02-16
Method and apparatus for verifying initial state equivalence of changed registers in retimed circuits Grant 10,706,203 - Iyer	2020-07-07
Method and apparatus for verifying structural correctness in retimed circuits Grant 10,671,790 - Iyer	2020-06-02
Fast Memory For Programmable Devices App 20200119736 - Weber; Scott Jeremy ; et al.	2020-04-16
Method and apparatus for reducing constraints during rewind structural verification of retimed circuits Grant 10,489,535 - Iyer , et al. Nov	2019-11-26
Method and apparatus for performing register retiming by utilizing native timing-driven constraints Grant 10,417,374 - Iyer Sept	2019-09-17
Discretizing gate sizes during numerical synthesis Grant 10,394,993 - Mottaez , et al. A	2019-08-27
Methods for verifying retimed circuits with delayed initialization Grant 10,372,850 - Iyer	2019-08-06
Methods And Apparatus To Insert Buffers In A Dataflow Graph App 20190229996 - ChoFleming, JR.; Kermin E. ; et al.	2019-07-25
Methods for bounding the number of delayed reset clock cycles for retimed circuits Grant 10,354,038 - Iyer July 16, 2	2019-07-16
Methods for incremental circuit design legalization during physical synthesis Grant 10,339,241 - Iyer , et al.	2019-07-02
Methods for reducing delay on integrated circuits by identifying candidate placement locations in a leveled graph Grant 10,318,686 - Dhar , et al.	2019-06-11
Method and apparatus for performing clock allocation for a system implemented on a programmable device Grant 10,303,202 - Adya , et al.	2019-05-28
Retiming with fixed power-up states Grant 10,296,701 - Iyer , et al.	2019-05-21
On-Die Aging Measurements for Dynamic Timing Modeling App 20190146028 - Subbareddy; Dheeraj ; et al.	2019-05-16
Retiming with programmable power-up states Grant 10,255,404 - Iyer , et al.	2019-04-09
Method And Apparatus For Performing Rewind Structural Verification Of Retimed Circuits Driven By A Plurality Of Clocks App 20190102497 - IYER; Mahesh A. ; et al.	2019-04-04
Methods And Apparatus For Reducing Reliability Degradation On An Integrated Circuit App 20190095571 - Cheng; Ning ; et al.	2019-03-28
Methods for minimizing logic overlap on integrated circuits Grant 10,242,144 - Adya , et al.	2019-03-26
Partial reconfiguration debugging using hybrid models Grant 10,235,485 - Iyer , et al.	2019-03-19
Configurable Wickless Capillary-driven Constrained Vapor Bubble (cvb) Heat Pipe Structures App 20190043782 - Basu; Sumita ; et al.	2019-02-07
Methods For Handling Integrated Circuit Dies With Defects App 20190044518 - Subbareddy; Dheeraj ; et al.	2019-02-07
Methods and apparatus for automatically implementing a compensating reset for retimed circuitry Grant 10,181,001 - Atsatt , et al. Ja	2019-01-15
Methods for delaying register reset for retimed circuits Grant 10,169,518 - Iyer J	2019-01-01
Integrated circuit retiming with selective modeling of flip-flop secondary signals Grant 10,162,918 - Iyer , et al. Dec	2018-12-25
Method and apparatus for performing rewind structural verification of retimed circuits driven by a plurality of clocks Grant 10,157,247 - Iyer , et al. Dec	2018-12-18
Methods For Performing Register Retiming With Hybrid Initial States App 20180349544 - Iyer; Mahesh A. ; et al.	2018-12-06
Sharing a JTAG interface among multiple partitions Grant 10,101,387 - Iyer , et al. October 16, 2	2018-10-16
Methods And Apparatus For Automatically Implementing A Compensating Reset For Retimed Circuitry App 20180218104 - Atsatt; Sean R. ; et al.	2018-08-02
Methods For Verifying Retimed Circuits With Delayed Initialization App 20180137226 - Iyer; Mahesh A.	2018-05-17
Methods For Reducing Delay On Integrated Circuits App 20180101624 - Dhar; Shounak ; et al.	2018-04-12
Sector-based clock routing methods and apparatus Grant 9,922,157 - Ebeling , et al. March 20, 2	2018-03-20
Method and Apparatus for Verifying Structural Correctness in Retimed Circuits App 20180039724 - Iyer; Mahesh A.	2018-02-08
Method and Apparatus for Performing Rewind Structural Verification of Retimed Circuits Driven by a Plurality of Clocks App 20180018417 - Iyer; Mahesh A. ; et al.	2018-01-18
Method and Apparatus for Reducing Constraints During Rewind Structural Verification of Retimed Circuits App 20180018416 - Iyer; Mahesh A. ; et al.	2018-01-18
Method and apparatus for verifying structural correctness in retimed circuits Grant 9,824,177 - Iyer November 21, 2	2017-11-21
Determining optimal gate sizes by using a numerical solver Grant 9,519,740 - Iyer , et al. December 13, 2	2016-12-13
Solving an optimization problem using a constraints solver Grant 9,454,626 - Iyer , et al. September 27, 2	2016-09-27
Solving a gate-sizing optimization problem using a constraints solver Grant 9,430,442 - Iyer , et al. August 30, 2	2016-08-30
Global timing modeling within a local context Grant 9,384,309 - Iyer , et al. July 5, 2	2016-07-05
Incremental slack margin propagation Grant 9,280,625 - Mottaez , et al. March 8, 2	2016-03-08
Incremental Slack Margin Propagation App 20160012166 - Mottaez; Amir H. ; et al.	2016-01-14
Efficient timing calculations in numerical sequential cell sizing and incremental slack margin propagation Grant 9,171,122 - Mottaez , et al. October 27, 2	2015-10-27
Hyper-concurrent optimization over multi-corner multi-mode scenarios Grant 9,064,073 - Mottaez , et al. June 23, 2	2015-06-23
Numerical area recovery Grant 8,990,750 - Iyer , et al. March 24, 2	2015-03-24
Numerical delay model for a technology library cell type Grant 8,977,999 - Iyer , et al. March 10, 2	2015-03-10
Robust numerical optimization for optimizing delay, area, and leakage power Grant 8,966,430 - Iyer , et al. February 24, 2	2015-02-24
Numerical Area Recovery App 20150040089 - Iyer; Mahesh A. ; et al.	2015-02-05
Solving An Optimization Problem Using A Constraints Solver App 20150040107 - Iyer; Mahesh A. ; et al.	2015-02-05
Robust Numerical Optimization For Optimizing Delay, Area, And Leakage Power App 20150040093 - Iyer; Mahesh A. ; et al.	2015-02-05
Discretizing Gate Sizes During Numerical Synthesis App 20150040090 - Mottaez; Amir H. ; et al.	2015-02-05
Solving A Gate-sizing Optimization Problem Using A Constraints Solver App 20150039664 - Iyer; Mahesh A. ; et al.	2015-02-05
Excluding library cells for delay optimization in numerical synthesis Grant 8,949,764 - Iyer , et al. February 3, 2	2015-02-03
Estimating optimal gate sizes by using numerical delay models Grant 8,843,871 - Mottaez , et al. September 23, 2	2014-09-23
Accurate approximation of the objective function for solving the gate-sizing problem using a numerical solver Grant 8,826,218 - Mottaez , et al. September 2, 2	2014-09-02
Modeling gate size range by using a penalty function in a numerical gate sizing framework Grant 8,826,217 - Mottaez , et al. September 2, 2	2014-09-02
Numerical Delay Model For A Technology Library Cell Type App 20140223400 - Iyer; Mahesh A. ; et al.	2014-08-07
Identifying candidate nets for buffering using numerical methods Grant 8,799,843 - Mottaez , et al. August 5, 2	2014-08-05
Numerical delay model for a technology library cell Grant 8,762,905 - Iyer , et al. June 24, 2	2014-06-24
Performing scenario reduction using a dominance relation on a set of corners Grant 8,707,241 - Mottaez , et al. April 22, 2	2014-04-22
Optimizing a circuit design for delay using load-and-slew-independent numerical delay models Grant 8,707,242 - Mottaez , et al. April 22, 2	2014-04-22
Sequential sizing in physical synthesis Grant 8,683,408 - Iyer , et al. March 25, 2	2014-03-25
Optimizing A Circuit Design For Delay Using Load-and-slew-independent Numerical Delay Models App 20140040851 - Mottaez; Amir H. ; et al.	2014-02-06
Modeling Gate Size Range In A Numerical Gate Sizing Framework App 20140033163 - Mottaez; Amir H. ; et al.	2014-01-30
Determining Optimal Gate Sizes By Using A Numerical Solver App 20140033162 - Iyer; Mahesh A. ; et al.	2014-01-30
Accurate Approximation Of The Objective Function For Solving The Gate-sizing Problem Using A Numerical Solver App 20140033161 - Mottaez; Amir H. ; et al.	2014-01-30
Estimating Optimal Gate Sizes By Using Numerical Delay Models App 20140007037 - Mottaez; Amir H. ; et al.	2014-01-02
Progressive circuit evaluation for circuit optimization Grant 8,621,408 - Iyer , et al. December 31, 2	2013-12-31
Incremental elmore delay calculation Grant 8,621,405 - Iyer , et al. December 31, 2	2013-12-31
Incremental Elmore Delay Calculation App 20130326449 - Iyer; Mahesh A. ; et al.	2013-12-05
Excluding Library Cells For Delay Optimization In Numerical Synthesis App 20130318488 - Iyer; Mahesh A. ; et al.	2013-11-28
Modeling transition effects for circuit optimization Grant 8,589,846 - Mottaez , et al. November 19, 2	2013-11-19
Delta-slack propagation for circuit optimization Grant 8,578,321 - Iyer , et al. November 5, 2	2013-11-05
Numerical Delay Model For A Technology Library Cell And/or A Technology Library Cell Type App 20130283222 - Iyer; Mahesh A. ; et al.	2013-10-24
Global leakage power optimization Grant 8,543,963 - Iyer , et al. September 24, 2	2013-09-24
Zone-based area recovery in electronic design automation Grant 8,527,927 - Walker , et al. September 3, 2	2013-09-03
Progressive Circuit Evaluation For Circuit Optimization App 20130145336 - Iyer; Mahesh A. ; et al.	2013-06-06
Modeling Transition Effects For Circuit Optimization App 20130145338 - Mottaez; Amir H. ; et al.	2013-06-06
Sequential Sizing In Physical Synthesis App 20130145331 - Iyer; Mahesh A. ; et al.	2013-06-06
Efficient Timing Calculations In Numerical Sequential Cell Sizing And Incremental Slack Margin Propagation App 20130145339 - Mottaez; Amir H. ; et al.	2013-06-06
Delta-slack Propagation For Circuit Optimization App 20130145337 - Iyer; Mahesh A. ; et al.	2013-06-06
Zone-based optimization framework for performing timing and design rule optimization Grant 8,418,116 - Walker , et al. April 9, 2	2013-04-09
Zone-based leakage power optimization Grant 8,316,339 - Iyer , et al. November 20, 2	2012-11-20
Density-based area recovery in electronic design automation Grant 8,266,570 - Walker , et al. September 11, 2	2012-09-11
Method and apparatus for determining a robustness metric for a circuit design Grant 8,239,800 - Iyer , et al. August 7, 2	2012-08-07
Performing Scenario Reduction Using A Dominance Relation On A Set Of Corners App 20120030641 - Mottaez; Amir H. ; et al.	2012-02-02
Hyper-concurrent Multi-scenario Optimization App 20120030642 - Mottaez; Amir H. ; et al.	2012-02-02
Global Timing Modeling Within A Local Context App 20110289464 - Iyer; Mahesh A. ; et al.	2011-11-24
Zone-based Area Recovery In Electronic Design Automation App 20110191731 - Walker; Robert ; et al.	2011-08-04
Density-based Area Recovery In Electronic Design Automation App 20110191738 - Walker; Robert ; et al.	2011-08-04
Method And Apparatus For Determining A Robustness Metric For A Circuit Design App 20110191732 - Iyer; Mahesh A. ; et al.	2011-08-04
Zone-based Optimization Framework App 20110191740 - Walker; Robert ; et al.	2011-08-04
Zone-based Leakage Power Optimization App 20110185334 - Iyer; Mahesh A. ; et al.	2011-07-28
Global Leakage Power Optimization App 20110185333 - Iyer; Mahesh A. ; et al.	2011-07-28
Interconnect-driven physical synthesis using persistent virtual routing Grant 7,853,915 - Saxena , et al. December 14, 2	2010-12-14
Interconnect-Driven Physical Synthesis Using Persistent Virtual Routing App 20090319977 - Saxena; Prashant ; et al.	2009-12-24
Adaptive cell separation and circuit changes driven by maximum capacitance rules Grant 6,397,169 - Shenoy , et al. May 28, 2	2002-05-28
Method for identifying untestable faults in logic circuits Grant 5,566,187 - Abramovici , et al. October 15, 1	1996-10-15

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