loadpatents
name:-0.028310060501099
name:-0.11998391151428
name:-0.00065302848815918
Iyengar; Vikram Patent Filings

Iyengar; Vikram

Patent Applications and Registrations

Patent applications and USPTO patent grants for Iyengar; Vikram.The latest application filed is for "systems and methods for single cell product path delay analysis".

Company Profile
0.32.32
  • Iyengar; Vikram - Pittsburgh PA US
  • Iyengar; Vikram - Essex Junction VT
  • Iyengar; Vikram - South Burlington VT
  • Iyengar; Vikram - S. Burlington VT
  • Iyengar; Vikram - Burlington VT
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Method and structure for multi-core chip product test and selective voltage binning disposition
Grant 9,557,378 - Bickford , et al. January 31, 2
2017-01-31
Systems and methods for single cell product path delay analysis
Grant 9,104,834 - Bickford , et al. August 11, 2
2015-08-11
Integrated circuit product yield optimization using the results of performance path testing
Grant 9,058,034 - Bickford , et al. June 16, 2
2015-06-16
Reducing power consumption during manufacturing test of an integrated circuit
Grant 9,043,180 - Iyengar , et al. May 26, 2
2015-05-26
Systems And Methods For Single Cell Product Path Delay Analysis
App 20150033199 - BICKFORD; Jeanne P. ;   et al.
2015-01-29
Systems and methods for single cell product path delay analysis
Grant 8,904,329 - Bickford , et al. December 2, 2
2014-12-02
Automatic generation of valid at-speed structural test (ASST) test groups
Grant 8,825,433 - Baalaji , et al. September 2, 2
2014-09-02
Systems And Methods For Single Cell Product Path Delay Analysis
App 20140195995 - Bickford; Jeanne P. ;   et al.
2014-07-10
Integrated Circuit Product Yield Optimization Using The Results Of Performance Path Testing
App 20140046466 - Bickford; Jeanne P. ;   et al.
2014-02-13
Method And Structure For Multi-core Chip Product Test And Selective Voltage Binning Disposition
App 20140024145 - BICKFORD; JEANNE P. ;   et al.
2014-01-23
Test path selection and test program generation for performance testing integrated circuit chips
Grant 8,543,966 - Bickford , et al. September 24, 2
2013-09-24
System yield optimization using the results of integrated circuit chip performance path testing
Grant 8,539,429 - Bickford , et al. September 17, 2
2013-09-17
Clock edge grouping for at-speed test
Grant 8,538,718 - Grise , et al. September 17, 2
2013-09-17
Reducing Power Consumption During Manufacturing Test Of An Integrated Circuit
App 20130211769 - Iyengar; Vikram ;   et al.
2013-08-15
Disposition of integrated circuits using performance sort ring oscillator and performance path testing
Grant 8,490,040 - Bickford , et al. July 16, 2
2013-07-16
Disposition Of Integrated Circuits Using Performance Sort Ring Oscillator And Performance Path Testing
App 20130125076 - Bickford; Jeanne P. ;   et al.
2013-05-16
Test Path Selection And Test Program Generation For Performance Testing Integrated Circuit Chips
App 20130125073 - Bickford; Jeanne P. ;   et al.
2013-05-16
Automatic Generation Of Valid At-speed Structural Test (asst) Test Groups
App 20130080108 - BAALAJI; Konda R. ;   et al.
2013-03-28
Method to test hold path faults using functional clocking
Grant 8,230,283 - Gillis , et al. July 24, 2
2012-07-24
At-speed Scan Enable Switching Circuit
App 20120176144 - Iyengar; Vikram ;   et al.
2012-07-12
System and method for automatically generating test patterns for at-speed structural test of an integrated circuit device using an incremental approach to reduce test pattern count
Grant 8,209,141 - Bassett , et al. June 26, 2
2012-06-26
Clock Edge Grouping For At-speed Test
App 20120150473 - Grise; Gary D. ;   et al.
2012-06-14
Hold transition fault model and test generation method
Grant 8,181,135 - Iyengar , et al. May 15, 2
2012-05-15
Online multiprocessor system reliability defect testing
Grant 8,176,362 - Denneau , et al. May 8, 2
2012-05-08
Integrated test waveform generator (TWG) and customer waveform generator (CWG), design structure and method
Grant 7,996,807 - Grise , et al. August 9, 2
2011-08-09
Method To Test Hold Path Faults Using Functional Clocking
App 20110154141 - Gillis; Pamela S. ;   et al.
2011-06-23
Hold Transition Fault Model and Test Generation Method
App 20110055650 - Iyengar; Vikram ;   et al.
2011-03-03
System and method for generating at-speed structural tests to improve process and environmental parameter space coverage
Grant 7,856,607 - Grise , et al. December 21, 2
2010-12-21
System And Method For Automatically Generating Test Patterns For At-speed Structural Test Of An Integrated Circuit Device Using An Incremental Approach To Reduce Test Pattern Count
App 20100235136 - Bassett; Robert W. ;   et al.
2010-09-16
Method of increasing path coverage in transition test generation
Grant 7,793,176 - Grise , et al. September 7, 2
2010-09-07
Identifying sequential functional paths for IC testing methods and system
Grant 7,784,000 - Grise , et al. August 24, 2
2010-08-24
Design structure for shutting off data capture across asynchronous clock domains during at-speed testing
Grant 7,779,375 - Grise , et al. August 17, 2
2010-08-17
Apparatus and method for selectively implementing launch off scan capability in at speed testing
Grant 7,721,170 - Grise , et al. May 18, 2
2010-05-18
Method and apparatus for shutting off data capture across asynchronous clock domains during at-speed testing
Grant 7,685,542 - Grise , et al. March 23, 2
2010-03-23
IC chip at-functional-speed testing with process coverage evaluation
Grant 7,620,921 - Foreman , et al. November 17, 2
2009-11-17
Integrated Test Waveform Generator (twg) And Customer Waveform Generator (cwg), Design Structure And Method
App 20090265677 - Grise; Gary D. ;   et al.
2009-10-22
Indentifying Sequential Functional Paths For Ic Testing Methods And System
App 20090240459 - Grise; Gary D. ;   et al.
2009-09-24
Online Multiprocessor System Reliability Defect Testing
App 20090241124 - Denneau; Monty M. ;   et al.
2009-09-24
Critical Path Selection For At-speed Test
App 20090150844 - Iyengar; Vikram ;   et al.
2009-06-11
System And Method For Generating At-speed Structural Tests To Improve Process And Environmental Parameter Space Coverage
App 20090119629 - Grise; Gary D. ;   et al.
2009-05-07
Testing of multiple asynchronous logic domains
Grant 7,529,294 - Grise , et al. May 5, 2
2009-05-05
Apparatus And Method For Selectively Implementing Launch Off Scan Capability In At Speed Testing
App 20090106608 - Grise; Gary D. ;   et al.
2009-04-23
Design Structure For Shutting Off Data Capture Across Asynchronous Clock Domains During At-speed Testing
App 20090102507 - Grise; Gary D. ;   et al.
2009-04-23
Ic Chip At-functional-speed Testing With Process Coverage Evaluation
App 20080270953 - Foreman; Eric A. ;   et al.
2008-10-30
Efficient scan chain insertion using broadcast scan for reduced bit collisions
Grant 7,441,171 - Iyengar October 21, 2
2008-10-21
Method of Increasing Path Coverage in Transition Test Generation
App 20080250279 - Grise; Gary D. ;   et al.
2008-10-09
Method For Automatic Test Pattern Generation For One Test Constraint At A Time
App 20080222472 - Grise; Gary D. ;   et al.
2008-09-11
Method And Apparatus For Shutting Off Data Capture Across Asynchronous Clock Domains During At-speed Testing
App 20080195905 - Grise; Gary D. ;   et al.
2008-08-14
Efficient Scan Chain Insertion Using Broadcast Scan For Reduced Bit Collisions
App 20070226564 - Iyengar; Vikram
2007-09-27
Testing Of Multiple Asynchronous Logic Domains
App 20070204194 - Grise; Gary Douglas ;   et al.
2007-08-30

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