Patent | Date |
---|
Signal transmit-receive device, circuit, and loopback test method Grant 7,216,269 - Baba , et al. May 8, 2 | 2007-05-08 |
Semiconductor integrated circuit Grant 6,937,068 - Nakayama , et al. August 30, 2 | 2005-08-30 |
Semiconductor device and electronic device Grant 6,911,734 - Kikuchi , et al. June 28, 2 | 2005-06-28 |
Semiconductor device and electronic device Grant 6,911,733 - Kikuchi , et al. June 28, 2 | 2005-06-28 |
Signal transmit-receive device, circuit, and loopback test method App 20040218665 - Baba, Takashige ;   et al. | 2004-11-04 |
Design method of semiconductor device Grant 6,760,895 - Ito , et al. July 6, 2 | 2004-07-06 |
Semiconductor integrated circuit and its fabrication method App 20040036497 - Nakayama, Michiaki ;   et al. | 2004-02-26 |
Semiconductor device and electronic device App 20030231088 - Kikuchi, Hiroshi ;   et al. | 2003-12-18 |
Semiconductor device and electronic device App 20030218238 - Kikuchi, Hiroshi ;   et al. | 2003-11-27 |
Design method of semiconductor device App 20030217344 - Ito, Yuko ;   et al. | 2003-11-20 |
Semiconductor integrated circuit and its fabrication method Grant 6,636,075 - Nakayama , et al. October 21, 2 | 2003-10-21 |
Method of computing wiring capacitance, method of computing signal propagation delay due to cross talk and computer-readable recording medium storing such computed data Grant 6,530,066 - Ito , et al. March 4, 2 | 2003-03-04 |
Semiconductor integrated circuit and its fabrication method App 20020070760 - Nakayama, Michiaki ;   et al. | 2002-06-13 |
Semiconductor integrated circuit and its fabrication method App 20010009383 - Nakayama, Michiaki ;   et al. | 2001-07-26 |
Semiconductor integrated circuit device including an improved separating groove arrangement Grant 5,661,329 - Hiramoto , et al. August 26, 1 | 1997-08-26 |
Semiconductor IC device having a RAM interposed between different logic sections and by-pass signal lines extending over the RAM for mutually connecting the logic sections Grant 5,477,067 - Isomura , et al. * December 19, 1 | 1995-12-19 |
Integrated circuit having alternate rows of logic cells and I/O cells Grant 5,341,049 - Shimizu , et al. August 23, 1 | 1994-08-23 |
Semiconductor device and semiconductor module having auxiliary high power supplying terminals Grant 5,306,948 - Yamada , et al. April 26, 1 | 1994-04-26 |
Semiconductor integrated circuit device having a gate array with a ram and by-pass signal lines which interconnect a logic section and I/O unit circuit of the gate array Grant 5,243,208 - Isomura , et al. * September 7, 1 | 1993-09-07 |
Semiconductor integrated circuit device having a gate array with a RAM and by-pass signal lines which interconnect a logic section and I/O unit circuit of the gate array Grant 5,103,282 - Isomura , et al. * April 7, 1 | 1992-04-07 |
Semiconductor device for a ram disposed on chip so as to minimize distances of signal paths between the logic circuits and memory circuit Grant 5,014,242 - Akimoto , et al. May 7, 1 | 1991-05-07 |
Semiconductor integrated circuit device Grant 4,959,704 - Isomura , et al. September 25, 1 | 1990-09-25 |
Semiconductor integrated circuit with dummy pedestals Grant 4,949,162 - Tamaki , et al. August 14, 1 | 1990-08-14 |
Articles having shape recovering properties and a method for using it Grant 4,831,094 - Stein , et al. May 16, 1 | 1989-05-16 |