ISHIOKA; Takashi

Patent Applications and Registrations

Patent applications and USPTO patent grants for ISHIOKA; Takashi.The latest application filed is for "printed wiring board and method for manufacturing printed wiring board".

Company Profile

3.8.9

ISHIOKA; Takashi - Namerikawa-shi JP
Ishioka; Takashi - Namerikawa JP
ISHIOKA; Takashi - Kanagawa JP
ISHIOKA; Takashi - Kawasaki-Shi JP
Ishioka; Takashi - Tokyo JP
Ishioka; Takashi - Kanagawa-ken JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Printed Wiring Board And Method For Manufacturing Printed Wiring Board App 20220232709 - NAGASE; Tomoya ; et al.	2022-07-21
Printed wiring board Grant 10,779,408 - Ishioka , et al. Sept	2020-09-15
Printed Wiring Board App 20200120799 - ISHIOKA; Takashi ; et al.	2020-04-16
Printed wiring board and method of producing the same Grant 9,402,309 - Saeki , et al. July 26, 2	2016-07-26
Printed Wiring Board And Method Of Producing The Same App 20150382458 - SAEKI; Shinri ; et al.	2015-12-31
Clock Tree Designing Apparatus And Clock Tree Designing Method App 20120240090 - SHIRAI; Toshiaki ; et al.	2012-09-20
Semiconductor Integrated Circuit, Method For Designing Semiconductor Integrated Circuit, And Computer Readable Recording Medium App 20110260764 - KITAHARA; Takeshi ; et al.	2011-10-27
Noise suppression circuit, ASIC, navigation apparatus, communication circuit, and communication apparatus having the same Grant 7,230,554 - Takeuchi , et al. June 12, 2	2007-06-12
Noise suppression circuit, ASIC, navigation apparatus, communication circuit, and communication apparatus having the same App 20060197695 - Takeuchi; Hideki ; et al.	2006-09-07
Method for distributing clock signals to flip-flop circuits Grant 7,075,336 - Kojima , et al. July 11, 2	2006-07-11
Noise suppression circuit, ASIC, navigation apparatus, communication circuit, and communication apparatus having the same Grant 7,064,691 - Takeuchi , et al. June 20, 2	2006-06-20
Method of automatic layout design for LSI, mask set and semiconductor integrated circuit manufactured by automatic layout design method, and recording medium storing automatic layout design program Grant 6,813,756 - Igarashi , et al. November 2, 2	2004-11-02
Method of automatic layout design for LSI, mask set and semiconductor integrated circuit manufactured by automatic layout design method, and recording medium storing automatic layout design program App 20030079194 - Igarashi, Mutsunori ; et al.	2003-04-24
Method of automatic layout design for LSI, mask set and semiconductor integrated circuit manufactured by automatic layout design method, and recording medium storing automatic layout design program Grant 6,546,540 - Igarashi , et al. April 8, 2	2003-04-08
Noise suppression circuit, asic, navigation apparatus, communication circuit, and communication apparatus having the same App 20030011500 - Takeuchi, Hideki ; et al.	2003-01-16
Method for distributing clock signals to flip-flop circuits App 20030014724 - Kojima, Naohito ; et al.	2003-01-16
Noise suppression circuit, ASIC, navigation apparatus communication circuit, and communication apparatus having the same Grant 6,459,331 - Takeuchi , et al. October 1, 2	2002-10-01

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