loadpatents
Patent applications and USPTO patent grants for Ishikawa; Yasuyuki.The latest application filed is for "method for refolding antibody, process for producing refolded antibody, refolded antibody, and uses thereof".
Patent | Date |
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Method for refolding antibody, process for producing refolded antibody, refolded antibody, and uses thereof Grant 9,850,316 - Kumada , et al. December 26, 2 | 2017-12-26 |
Method For Refolding Antibody, Process For Producing Refolded Antibody, Refolded Antibody, And Uses Thereof App 20150376297 - Kumada; Yoichi ;   et al. | 2015-12-31 |
Apparatus And Method For Manufacturing Absorbent Article App 20120073760 - Hamada; Akira ;   et al. | 2012-03-29 |
Semiconductor integrated circuit device for providing series regulator Grant 7,906,946 - Taguchi , et al. March 15, 2 | 2011-03-15 |
Frequency-multiplied clock signal output circuit Grant 7,560,996 - Ishikawa , et al. July 14, 2 | 2009-07-14 |
Microcomputer with mode decoder operable upon receipt of either power-on or external reset signal Grant 7,467,294 - Matsuoka , et al. December 16, 2 | 2008-12-16 |
Semiconductor integrated circuit device for providing series regulator App 20080303497 - Taguchi; Shinichirou ;   et al. | 2008-12-11 |
Frequency-multiplied clock signal output circuit App 20080084250 - Ishikawa; Yasuyuki ;   et al. | 2008-04-10 |
Reset detection circuit in semiconductor integrated circuit Grant 7,313,048 - Ishikawa , et al. December 25, 2 | 2007-12-25 |
Reset detection circuit in semiconductor integrated circuit App 20070210834 - Ishikawa; Yasuyuki ;   et al. | 2007-09-13 |
Clamp circuit device Grant 7,248,092 - Misawa , et al. July 24, 2 | 2007-07-24 |
Integrated circuit device having clock signal output circuit Grant 7,221,206 - Misawa , et al. May 22, 2 | 2007-05-22 |
Method and system for designing an integrated circuit with reduced noise Grant 7,203,921 - Ishikawa , et al. April 10, 2 | 2007-04-10 |
Microcomputer App 20060107082 - Matsuoka; Toshihiko ;   et al. | 2006-05-18 |
Integrated circuit device having clock signal output circuit App 20050206461 - Misawa, Katsutoyo ;   et al. | 2005-09-22 |
Clamp circuit device App 20050206429 - Misawa, Katsutoyo ;   et al. | 2005-09-22 |
Method and system for designing an integrated circuit with reduced noise App 20040168142 - Ishikawa, Yasuyuki ;   et al. | 2004-08-26 |
Semiconductor integrated circuit device Grant 6,677,781 - Ishikawa , et al. January 13, 2 | 2004-01-13 |
Semiconductor integrated circuit device and method for mounting circuit blocks in semiconductor integrated circuit device Grant 6,657,318 - Ishikawa , et al. December 2, 2 | 2003-12-02 |
Semiconductor integrated circuit device App 20030085757 - Ichikawa, Kouji ;   et al. | 2003-05-08 |
Semiconductor integrated circuit device App 20020190578 - Ishikawa, Yasuyuki ;   et al. | 2002-12-19 |
Semiconductor integrated circuit device and method for mounting circuit blocks in semiconductor integrated circuit device App 20020014915 - Ishikawa, Yasuyuki ;   et al. | 2002-02-07 |
Ophthalmic instrument Grant 4,678,297 - Ishikawa , et al. July 7, 1 | 1987-07-07 |
Eye examining instrument Grant 4,533,222 - Ishikawa August 6, 1 | 1985-08-06 |
Auto eye-refractometer Grant 4,421,391 - Matsumura , et al. December 20, 1 | 1983-12-20 |
Apparatus for measuring the refractive power of the eye Grant 4,376,573 - Matsumura , et al. March 15, 1 | 1983-03-15 |
Automatic eye-refractometer Grant 4,372,655 - Matsumura , et al. February 8, 1 | 1983-02-08 |
Eye refractometer Grant 4,293,198 - Kohayakawa , et al. October 6, 1 | 1981-10-06 |
NCAGE Code | 3GGV1 | ISHIKAWA YASUYUKI |
CAGE Code | 3GGV1 | ISHIKAWA, YASUYUKI YASUYUKI ISHIKAWA |
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