Irrinki; V. Swamy

Patent Applications and Registrations

Patent applications and USPTO patent grants for Irrinki; V. Swamy.The latest application filed is for "detecting faults in dual port fifo memories".

Company Profile

0.15.0

Irrinki; V. Swamy - Milpitas CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Detecting faults in dual port FIFO memories Grant 6,757,854 - Zhao , et al. June 29, 2	2004-06-29
Parallel testing of a multiport memory Grant 6,681,358 - Karimi , et al. January 20, 2	2004-01-20
Asynchronous bist for embedded multiport memories Grant 6,671,842 - Phan , et al. December 30, 2	2003-12-30
Detecting interport faults in multiport static memories Grant 6,550,032 - Zhao , et al. April 15, 2	2003-04-15
Testing methodology for embedded memories using built-in self repair and identification circuitry Grant 6,367,042 - Phan , et al. April 2, 2	2002-04-02
Built-in self-test unit having a reconfigurable data retention test Grant 6,255,836 - Schwarz , et al. July 3, 2	2001-07-03
Redundancy analysis for embedded memories with built-in self test and built-in self repair Grant 6,067,262 - Irrinki , et al. May 23, 2	2000-05-23
Test circuitry for determining the defect density of a semiconductor process as a function of individual metal layers Grant 6,061,814 - Sugasawara , et al. May 9, 2	2000-05-09
Method of testing memory operations employing self-repair circuitry and permanently disabling memory locations Grant 5,987,632 - Irrinki , et al. November 16, 1	1999-11-16
Memory cell capable of storing more than two logic states by using different via resistances Grant 5,982,659 - Irrinki , et al. November 9, 1	1999-11-09
Built in self repair for DRAMs using on-chip temperature sensing and heating Grant 5,956,350 - Irrinki , et al. September 21, 1	1999-09-21
Memory circuit and method for multivalued logic storage by process variations Grant 5,867,423 - Kapoor , et al. February 2, 1	1999-02-02
Ram cell capable of storing 3 logic states Grant 5,847,990 - Irrinki , et al. December 8, 1	1998-12-08
Memory system including an on-chip temperature sensor for regulating the refresh rate of a DRAM array Grant 5,784,328 - Irrinki , et al. July 21, 1	1998-07-21
Memory cell capable of storing more than two logic states by using programmable resistances Grant 5,761,110 - Irrinki , et al. June 2, 1	1998-06-02

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.