Irish; John D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Irish; John D..The latest application filed is for "integrated circuit and data processing system supporting address aliasing in an accelerator".

Company Profile

7.29.33

Irish; John D. - Rochester MN
Irish; John D. - NW Rochester MN US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Translation invalidation in a translation cache serving an accelerator Grant 11,113,204 - Blaner , et al. September 7, 2	2021-09-07
Integrated circuit and data processing system supporting address aliasing in an accelerator Grant 11,030,110 - Siegel , et al. June 8, 2	2021-06-08
Integrated circuit and data processing system supporting attachment of a real address-agnostic accelerator Grant 10,846,235 - Blaner , et al. November 24, 2	2020-11-24
Integrated circuit and data processing system having a configurable cache directory for an accelerator Grant 10,761,995 - Blaner , et al. Sep	2020-09-01
Accelerator memory coherency with single state machine Grant 10,613,979 - Valk , et al.	2020-04-07
Techniques for faster loading of data for accelerators Grant 10,528,399 - Fredrickson , et al. J	2020-01-07
Integrated Circuit And Data Processing System Having A Configurable Cache Directory For An Accelerator App 20190332549 - BLANER; BARTHOLOMEW ; et al.	2019-10-31
Integrated Circuit And Data Processing System Supporting Address Aliasing In An Accelerator App 20190332551 - SIEGEL; MICHAEL S. ; et al.	2019-10-31
Integrated Circuit And Data Processing System Supporting Attachment Of A Real Address-agnostic Accelerator App 20190332537 - BLANER; BARTHOLOMEW ; et al.	2019-10-31
Translation Invalidation In A Translation Cache Serving An Accelerator App 20190332548 - BLANER; BARTHOLOMEW ; et al.	2019-10-31
Techniques For Faster Loading Of Data For Accelerators App 20190213050 - FREDRICKSON; Mark S. ; et al.	2019-07-11
Accelerator Memory Coherency With Single State Machine App 20190163633 - Valk; Kenneth M. ; et al.	2019-05-30
Non-serialized push instruction for pushing a message payload from a sending thread to a receiving thread Grant 9,778,933 - Arimilli , et al. October 3, 2	2017-10-03
Non-serialized push instruction for pushing a message payload from a sending thread to a receiving thread Grant 9,766,890 - Arimilli , et al. September 19, 2	2017-09-19
Addressing for inter-thread push communication Grant 9,684,551 - Arimilli , et al. June 20, 2	2017-06-20
Addressing for inter-thread push communication Grant 9,678,812 - Arimilli , et al. June 13, 2	2017-06-13
Push instruction for pushing a message payload from a sending thread to a receiving thread Grant 9,575,825 - Arimilli , et al. February 21, 2	2017-02-21
Push instruction for pushing a message payload from a sending thread to a receiving thread Grant 9,569,293 - Arimilli , et al. February 14, 2	2017-02-14
Push Instruction For Pushing A Message Payload From A Sending Thread To A Receiving Thread App 20160179591 - ARIMILLI; LAKSHMINARAYANA B. ; et al.	2016-06-23
Addressing For Inter-thread Push Communication App 20160179592 - ARIMILLI; LAKSHMINARAYANA B. ; et al.	2016-06-23
Addressing For Inter-thread Push Communication App 20160179590 - ARIMILLI; LAKSHMINARAYANA B. ; et al.	2016-06-23
Non-serialized Push Instruction For Pushing A Message Payload From A Sending Thread To A Receiving Thread App 20160179518 - ARIMILLI; LAKSHMINARAYANA B. ; et al.	2016-06-23
Non-serialized Push Instruction For Pushing A Message Payload From A Sending Thread To A Receiving Thread App 20160179517 - ARIMILLI; LAKSHMINARAYANA B. ; et al.	2016-06-23
Push Instruction For Pushing A Message Payload From A Sending Thread To A Receiving Thread App 20160179593 - ARIMILLI; LAKSHMINARAYANA B. ; et al.	2016-06-23
Hardware-assisted interthread push communication Grant 9,342,387 - Arimilli , et al. May 17, 2	2016-05-17
Hardware-assisted interthread push communication Grant 9,286,148 - Arimilli , et al. March 15, 2	2016-03-15
Methods and apparatus for handling a cache miss Grant 8,589,630 - Irish , et al. November 19, 2	2013-11-19
Resource allocation management using IOC token requestor logic Grant 8,490,102 - Handlogten , et al. July 16, 2	2013-07-16
Methods and apparatus for handling a cache miss Grant 8,327,075 - Irish , et al. December 4, 2	2012-12-04
Methods And Apparatus For Handling A Cache Miss App 20120272009 - Irish; John D. ; et al.	2012-10-25
Method and apparatus for allowing uninterrupted address translations while performing address translation cache invalidates and other cache operations Grant 8,127,082 - McBride , et al. February 28, 2	2012-02-28
Memory command and address conversion between an XDR interface and a double data rate interface Grant 7,757,040 - Bellows , et al. July 13, 2	2010-07-13
I/O address translation method for specifying a relaxed ordering for I/O accesses Grant 7,721,023 - Irish , et al. May 18, 2	2010-05-18
Pseudo LRU algorithm for hint-locking during software and hardware address translation cache miss handling modes Grant 7,716,423 - Irish , et al. May 11, 2	2010-05-11
Handling Concurrent Address Translation Cache Misses And Hits Under Those Misses While Maintaining Command Order App 20090187695 - Irish; John D. ; et al.	2009-07-23
Handling concurrent address translation cache misses and hits under those misses while maintaining command order Grant 7,539,840 - Irish , et al. May 26, 2	2009-05-26
Methods and Apparatus for Issuing Commands on a Bus App 20080189501 - Irish; John D. ; et al.	2008-08-07
Memory Command and Address Conversion Between an XDR Interface and a Double Data Rate Interface App 20080183925 - Bellows; Mark D. ; et al.	2008-07-31
Methods and Apparatus for Combining Commands Prior to Issuing the Commands on a Bus App 20080126641 - Irish; John D. ; et al.	2008-05-29
Methods and Apparatus for Scheduling Prioritized Commands on a Bus App 20080059672 - Irish; John D. ; et al.	2008-03-06
Method and Apparatus for Handling Concurrent Address Translation Cache Misses and Hits Under Those Misses While Maintaining Command Order App 20070283121 - Irish; John D. ; et al.	2007-12-06
Hardware Assisted Exception for Software Miss Handling of an I/O Address Translation Cache Miss App 20070260754 - Irish; John D. ; et al.	2007-11-08
Data transfer buffer control for performance App 20070198754 - Hill; David W. ; et al.	2007-08-23
Pseudo LRU algorithm for hint-locking during software and hardware address translation cache miss handling modes App 20070186046 - Irish; John D. ; et al.	2007-08-09
Method for cache hit under miss collision handling App 20070180157 - Irish; John D. ; et al.	2007-08-02
Method and apparatus for allowing uninterrupted address translations while performing address translation cache invalidates and other cache operations App 20070180195 - McBride; Chad B. ; et al.	2007-08-02
Method for completing IO commands after an IO translation miss App 20070180156 - Irish; John D. ; et al.	2007-08-02
Method for command list ordering after multiple cache misses App 20070180158 - Irish; John D. ; et al.	2007-08-02
I/O address translation blocking in a secure system during power-on-reset App 20070180269 - Irish; John D. ; et al.	2007-08-02
Methods and apparatus for handling a cache miss App 20070136532 - Irish; John D. ; et al.	2007-06-14
I/O address translation apparatus and method for specifying a relaxed ordering for I/O accesses App 20070130372 - Irish; John D. ; et al.	2007-06-07
Methods and apparatus for maintaining coherency in a multi-processor system Grant 7,089,387 - Ganfield , et al. August 8, 2	2006-08-08
Resource allocation management App 20060026598 - Handlogten; Glen H. ; et al.	2006-02-02
Cache prefetching Grant 6,922,753 - Brown , et al. July 26, 2	2005-07-26
Methods and apparatus for allocating memory App 20050071595 - Irish, John D. ; et al.	2005-03-31
Methods and apparatus for maintaining coherency in a multi-processor system App 20050044328 - Ganfield, Paul A. ; et al.	2005-02-24
Cache prefetching App 20040064648 - Brown, Jeffrey D. ; et al.	2004-04-01
Peer-to-peer cache moves in a multiprocessor data processing system Grant 6,314,491 - Freerksen , et al. November 6, 2	2001-11-06
Multi-entry fully associative transition cache Grant 6,000,011 - Freerksen , et al. December 7, 1	1999-12-07
System for aligning bytes of variable multi-bytes length operand based on alu byte length and a number of unprocessed byte data Grant 5,168,571 - Hoover , et al. December 1, 1	1992-12-01

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