loadpatents
name:-0.0025200843811035
name:-0.030156850814819
name:-0.0045619010925293
Ip; Chung-Wah Norris Patent Filings

Ip; Chung-Wah Norris

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ip; Chung-Wah Norris.The latest application filed is for "manipulation of traces for debugging a circuit design".

Company Profile
2.33.3
  • Ip; Chung-Wah Norris - Cupertino CA
  • Ip; Chung-Wah Norris - Fremont CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
System, method, and computer program product for displaying debugging during a formal verification
Grant 10,783,304 - Roque , et al. Sept
2020-09-22
System, method, and computer program product for displaying multiple traces while debugging during a formal verification
Grant 10,635,768 - Roque , et al.
2020-04-28
Methods, systems, and computer program product for connectivity verification of electronic designs
Grant 10,409,945 - Ip , et al. Sept
2019-09-10
Methods, systems, and articles of manufacture for X-behavior verification of an electronic design
Grant 10,380,295 - Ip , et al. A
2019-08-13
System, method, and computer program product for capture and reuse in a debug workspace
Grant 10,331,547 - Lin , et al.
2019-06-25
Method and system for implementing selective transformation for low power verification
Grant 10,162,917 - Peixoto , et al. Dec
2018-12-25
Methods, systems, and articles of manufacture for graph-driven verification and debugging of an electronic design
Grant 10,094,875 - Lin , et al. October 9, 2
2018-10-09
Method and system for automated debugging of a device under test
Grant 9,928,328 - Cohen , et al. March 27, 2
2018-03-27
Methods, systems, and articles of manufacture for automatic extraction of connectivity information for implementation of electronic designs
Grant 9,734,278 - Purri , et al. August 15, 2
2017-08-15
Methods, systems, and articles of manufacture for trace warping for electronic designs
Grant 9,659,142 - Coelho, Jr. , et al. May 23, 2
2017-05-23
Isolating differences between revisions of a circuit design
Grant 9,477,802 - Ip , et al. October 25, 2
2016-10-25
Manipulation of traces for debugging a circuit design
Grant 9,081,927 - Coelho, Jr. , et al. July 14, 2
2015-07-14
Manipulation Of Traces For Debugging A Circuit Design
App 20150100932 - Coelho, JR.; Claudionor Jose Nunes ;   et al.
2015-04-09
Manipulation Of Traces For Debugging Behaviors Of A Circuit Design
App 20150100933 - Coelho, JR.; Claudionor Jose Nunes ;   et al.
2015-04-09
Visualization Constraints For Circuit Designs
App 20150095862 - Ip; Chung-Wah Norris ;   et al.
2015-04-02
Manipulation of traces for debugging behaviors of a circuit design
Grant 8,990,745 - Coelho , et al. March 24, 2
2015-03-24
Visualization constraints for circuit designs
Grant 8,984,461 - Ip , et al. March 17, 2
2015-03-17
Constraining traces in formal verification
Grant 8,863,049 - Lundgren , et al. October 14, 2
2014-10-14
Indexing behaviors and recipes of a circuit design
Grant 8,831,925 - Kranen , et al. September 9, 2
2014-09-09
Indexing behaviors and recipes of a circuit design
Grant 8,731,894 - Kranen , et al. May 20, 2
2014-05-20
Comprehending waveforms of a circuit design
Grant 8,630,824 - Ip , et al. January 14, 2
2014-01-14
Comprehending a circuit design
Grant 8,527,911 - Kranen , et al. September 3, 2
2013-09-03
Generalizing and inferring behaviors of a circuit design
Grant 8,205,187 - Coelho , et al. June 19, 2
2012-06-19
Extracting, visualizing, and acting on inconsistencies between a circuit design and its abstraction
Grant 7,895,552 - Singhal , et al. February 22, 2
2011-02-22
Managing formal verification complexity of designs with multiple related counters
Grant 7,647,572 - Ip , et al. January 12, 2
2010-01-12
Interactive analysis and debugging of a circuit design during functional verification of the circuit design
Grant 7,506,288 - Ip , et al. March 17, 2
2009-03-17
System and method for determining and identifying signals that are relevantly determined by a selected signal in a circuit design
Grant 7,437,694 - Loh , et al. October 14, 2
2008-10-14
System and method for identifying design efficiency and effectiveness parameters for verifying properties of a circuit model
Grant 7,159,198 - Ip , et al. January 2, 2
2007-01-02
System and method for guiding and optimizing formal verification for a circuit design
Grant 7,065,726 - Singhal , et al. June 20, 2
2006-06-20
Method and apparatus for transforming test stimulus
Grant 6,915,248 - Ip July 5, 2
2005-07-05

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