INUI; SHIGETO

Patent Applications and Registrations

Patent applications and USPTO patent grants for INUI; SHIGETO.The latest application filed is for "wire verification method, wire verification apparatus and wire verification program for semiconductor integrated circuit".

Company Profile

0.6.5

INUI; SHIGETO - Tokyo JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Wire Verification Method, Wire Verification Apparatus And Wire Verification Program For Semiconductor Integrated Circuit App 20120136599 - INUI; SHIGETO	2012-05-31
Logic circuit, logic circuit design method, logic circuit design system, and logic circuit design program Grant 8,065,645 - Inui , et al. November 22, 2	2011-11-22
Dual rail domino circuit and logic circuit Grant 7,893,721 - Inui February 22, 2	2011-02-22
Dual Rail Domino Circuit, Domino Circuit, And Logic Circuit App 20100045344 - Inui; Shigeto	2010-02-25
Logic Circuit, Logic Circuit Design Method, Logic Circuit Design System, And Logic Circuit Design Program App 20070234242 - Inui; Shigeto ; et al.	2007-10-04
Logic circuit, logic circuit design method, logic circuit design system, and logic circuit design program Grant 7,236,006 - Inui , et al. June 26, 2	2007-06-26
Logic circuit, logic circuit design method, logic circuit design system, and logic circuit design program App 20050212578 - Inui, Shigeto ; et al.	2005-09-29
Divider Grant 6,847,986 - Inui January 25, 2	2005-01-25
Divider App 20010025293 - Inui, Shigeto	2001-09-27
Dynamic logic circuit Grant 6,060,910 - Inui May 9, 2	2000-05-09
Carry look ahead addition method and carry look ahead addition device Grant 5,477,480 - Inui December 19, 1	1995-12-19

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