Trademark applications and grants for Intrinsity Inc. Intrinsity Inc has 14 trademark applications. The latest application filed is for "FAST14"
Patent Application | Date |
---|---|
Method for Preparing Re-Architected Designs for Sequential Equivalence Checking 20110214097 - 13/128153 Nodine; Mark H. | 2011-09-01 |
Method For Piecewise Hierarchical Sequential Verification 20110214096 - 13/127936 Sheeley; Nathan Francis ;   et al. | 2011-09-01 |
GENERATING TEST BENCHES FOR PRE-SILICON VALIDATION OF RETIMED COMPLEX IC DESIGNS AGAINST A REFERENCE DESIGN 20100045333 - 12/526691 Nodine; Mark H. | 2010-02-25 |
Physical realization of dynamic logic using parameterized tile partitioning 20050060128 - 10/738278 Reed, Jeffrey B. ;   et al. | 2005-03-17 |
Expansion syntax 20040139423 - 10/738281 Boehm, Fritz A. ;   et al. | 2004-07-15 |
SEC | 0001414423 | Intrinsity Inc of TEXAS |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.