Interrante; Marcus E.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Interrante; Marcus E..The latest application filed is for "integrated circuit (ic) device package lid attach utilizing nano particle metallic paste".

Company Profile

8.12.8

Interrante; Marcus E. - Ulster NY
Interrante; Marcus E. - Highland NY
Interrante; Marcus E. - New Paltz NY
INTERRANTE; MARCUS E - New Paltz NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Integrated circuit (IC) device package lid attach utilizing nano particle metallic paste Grant 11,164,804 - Arvin , et al. November 2, 2	2021-11-02
Multi integrated circuit chip carrier package Grant 10,978,314 - Interrante , et al. April 13, 2	2021-04-13
Integrated Circuit (IC) Device Package Lid Attach Utilizing Nano Particle Metallic Paste App 20210028079 - Arvin; Charles L. ; et al.	2021-01-28
Managing thermal warpage of a laminate Grant 10,832,987 - Arvin , et al. November 10, 2	2020-11-10
Heterogeneous thermal interface material for corner and or edge degradation mitigation Grant 10,804,181 - Interrante , et al. October 13, 2	2020-10-13
Heterogeneous Thermal Interface Material for Corner and or Edge Degradation Mitigation App 20200294880 - Interrante; Marcus E. ; et al.	2020-09-17
Multi Integrated Circuit Chip Carrier Package App 20200135495 - Interrante; Marcus E. ; et al.	2020-04-30
Multi integrated circuit chip carrier package Grant 10,541,156 - Interrante , et al. Ja	2020-01-21
Managing Thermal Warpage Of A Laminate App 20190295921 - Arvin; Charles L. ; et al.	2019-09-26
Reducing directional stress in an orthotropic encapsulation member of an electronic package Grant 9,583,408 - Interrante , et al. February 28, 2	2017-02-28
Reducing Directional Stress In An Orthotropic Encapsulation Member Of An Electronic Package App 20170053845 - INTERRANTE; Marcus E. ; et al.	2017-02-23
Thermal hot spot cooling for semiconductor devices Grant 9,401,315 - Bodenweber , et al. July 26, 2	2016-07-26
Electronic module assembly with patterned adhesive array Grant 9,293,439 - Blackshear , et al. March 22, 2	2016-03-22
3D bond and assembly process for severely bowed interposer die Grant 9,224,712 - Interrante , et al. December 29, 2	2015-12-29
3d Bond And Assembly Process For Severely Bowed Interposer Die App 20150228614 - INTERRANTE; MARCUS E ; et al.	2015-08-13
Electronic module assembly with patterned adhesive array Grant 9,093,563 - Blackshear , et al. July 28, 2	2015-07-28
Electronic Module Assembly With Patterned Adhesive Array App 20150093859 - Blackshear; Edmund ; et al.	2015-04-02
Electronic Module Assembly With Patterned Adhesive Array App 20150014836 - Blackshear; Edmund ; et al.	2015-01-15
Uniform solder reflow fixture Grant 8,444,043 - Bernier , et al. May 21, 2	2013-05-21

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