loadpatents
name:-0.017933130264282
name:-0.028926134109497
name:-0.0016269683837891
Inoue; Aiichiro Patent Filings

Inoue; Aiichiro

Patent Applications and Registrations

Patent applications and USPTO patent grants for Inoue; Aiichiro.The latest application filed is for "multi-chip module".

Company Profile
0.27.13
  • Inoue; Aiichiro - Kawasaki N/A JP
  • Inoue; Aiichiro - Kanagawa JP
  • Inoue; Aiichiro - Yokohama JP
  • Inoue; Aiichiro - Hiratsuka JP
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Information processing apparatus, memory control method, and memory control device utilizing local and global snoop control units to maintain cache coherency
Grant 8,464,004 - Sugizaki , et al. June 11, 2
2013-06-11
Multi-chip module
Grant 8,446,020 - Koide , et al. May 21, 2
2013-05-21
Multi-chip Module
App 20110089579 - KOIDE; Masateru ;   et al.
2011-04-21
Return target address prediction by moving entry pointer to return stack popped at completion to deeper one at return instruction fetch
Grant 7,925,870 - Ukai , et al. April 12, 2
2011-04-12
Program counter control method and processor thereof for controlling simultaneous execution of a plurality of instructions including branch instructions using a branch prediction mechanism and a delay instruction for branching
Grant 7,765,387 - Sunayama , et al. July 27, 2
2010-07-27
Instruction control method and processor to process instructions by out-of-order processing using delay instructions for branching
Grant 7,603,545 - Sunayama , et al. October 13, 2
2009-10-13
Information processing device, memory control method, and memory control device
App 20090240893 - Sugizaki; Go ;   et al.
2009-09-24
Predicted return address from return stack entry designated by computation unit with multiple inputs including return hit flag and re-fetch signal
Grant 7,350,062 - Ukai , et al. March 25, 2
2008-03-25
Instruction execution apparatus comprising a commit stack entry unit
Grant 7,278,010 - Akizuki , et al. October 2, 2
2007-10-02
Pre-fetch control device, data processing apparatus and pre-fetch control method
Grant 7,246,204 - Shirahige , et al. July 17, 2
2007-07-17
Instruction processing device and method for controlling branch instruction accompanied by mode change
Grant 7,036,003 - Sunayama , et al. April 25, 2
2006-04-25
Memory access device and method using address translation history table
Grant 6,993,638 - Ukai , et al. January 31, 2
2006-01-31
Predicted return address selection upon matching target in branch history table with entries in return address stack
App 20050278516 - Ukai, Masaki ;   et al.
2005-12-15
Apparatus and method of controlling instruction fetch
App 20050198480 - Ukai, Masaki ;   et al.
2005-09-08
Pre-prefetching target of following branch instruction based on past history
Grant 6,912,650 - Ukai , et al. June 28, 2
2005-06-28
Device predicting a branch of an instruction equivalent to a subroutine return and a method thereof
Grant 6,898,698 - Sunayama , et al. May 24, 2
2005-05-24
Branch instruction execution control apparatus
Grant 6,851,043 - Inoue February 1, 2
2005-02-01
Instruction control apparatus and method using micro program
Grant 6,789,185 - Gomyo , et al. September 7, 2
2004-09-07
Instruction processing apparatus using a microprogram that implements a re-reading operation by controlling early loading of instructions
Grant 6,754,814 - Narita , et al. June 22, 2
2004-06-22
Instruction execution apparatus
App 20040006684 - Akizuki, Yasunobu ;   et al.
2004-01-08
Program counter control method and processor
App 20040003207 - Sunayama, Ryuichi ;   et al.
2004-01-01
Pre-fetch control device, data processing apparatus and pre-fetch control method
App 20040003179 - Shirahige, Yuji ;   et al.
2004-01-01
Instruction control method and processor
App 20040003214 - Sunayama, Ryuichi ;   et al.
2004-01-01
Virtual storage address space access control
Grant 6,606,696 - Kawano , et al. August 12, 2
2003-08-12
Detection of overwrite modification by preceding instruction possibility of fetched instruction code using fetched instructions counter and store target address
Grant 6,571,329 - Ukai , et al. May 27, 2
2003-05-27
Predicted return address selection upon matching target in branch history table with entries in return address stack
App 20030097549 - Ukai, Masaki ;   et al.
2003-05-22
Instruction control apparatus for loading plurality of instructions into execution stage
Grant 6,530,013 - Hara , et al. March 4, 2
2003-03-04
Predicted return address selection upon matching target in branch history table with entries in return address stack
Grant 6,530,016 - Ukai , et al. March 4, 2
2003-03-04
Instruction processing apparatus
Grant 6,502,186 - Inoue December 31, 2
2002-12-31
Memory access device and method using address translation history table
App 20020184430 - Ukai, Masaki ;   et al.
2002-12-05
Processor Performing Parallel Operations Subject To Operand Register Interference Using Operand History Storage
App 20020049895 - INOUE, AIICHIRO
2002-04-25
Apparatus and method of controlling instruction fetch
App 20010027515 - Ukai, Masaki ;   et al.
2001-10-04
Instruction processing apparatus
App 20010004756 - Inoue, Aiichiro
2001-06-21
Virtual storage address space access control system including auxiliary translation lookaside buffer
Grant 5,923,864 - Inoue July 13, 1
1999-07-13
Method and apparatus overcoming delay introduced by instruction interlocking in pipelined instruction execution
Grant 5,548,736 - Asakawa , et al. August 20, 1
1996-08-20
Circuit for executing conditional branch instructions in pipeline process
Grant 5,408,620 - Asakawa , et al. April 18, 1
1995-04-18
System and method for serialization control of accesses to a common main storage
Grant 5,297,267 - Inoue March 22, 1
1994-03-22
Centralized command transfer control system for connecting processors which independently send and receive commands
Grant 4,852,021 - Inoue , et al. July 25, 1
1989-07-25

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