Inapac Technology, Inc.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Inapac Technology, Inc..The latest application filed is for "memory accessing circuit system".

Company Profile

0.30.10

Inapac Technology, Inc. - San Jose CA
Inapac Technology, Inc. -
Inapac Technology, Inc - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Trademarks

Patent Activity

Patent	Date
Memory accessing circuit system Grant 7,466,603 - Ong December 16, 2	2008-12-16
Shared memory bus architecture for system with processor and memory units Grant 7,466,160 - Ong , et al. December 16, 2	2008-12-16
Integrated circuit testing module including address generator Grant 7,446,551 - Ong November 4, 2	2008-11-04
Electronic device having an interface supported testing mode Grant 7,443,188 - Ong October 28, 2	2008-10-28
Architecture and method for testing of an integrated circuit device Grant 7,444,575 - Ong October 28, 2	2008-10-28
Component testing and recovery Grant 7,404,117 - Ong , et al. July 22, 2	2008-07-22
Integrated circuit testing module including data compression Grant 7,370,256 - Ong May 6, 2	2008-05-06
Integrated circuit testing module including data generator Grant 7,365,557 - Ong April 29, 2	2008-04-29
Memory accessing circuit system App 20080089139 - Ong; Adrian E.	2008-04-17
Electronic device having an interface supported testing mode App 20080061811 - Ong; Adrian E.	2008-03-13
Internally generating patterns for testing in an integrated circuit device Grant 7,313,740 - Ong December 25, 2	2007-12-25
Electronic device having an interface supported testing mode Grant 7,309,999 - Ong December 18, 2	2007-12-18
Integrated circuit testing module including command driver Grant 7,310,000 - Ong December 18, 2	2007-12-18
Integrated circuit test array including test module Grant 7,307,442 - Ong December 11, 2	2007-12-11
Isolating electric paths in semiconductor device packages App 20070241443 - Ong; Adrian E. ; et al.	2007-10-18
Delay lock loop delay adjusting method and apparatus Grant 7,269,524 - Ong , et al. September 11, 2	2007-09-11
Integrated circuit testing module Grant 7,265,570 - Ong September 4, 2	2007-09-04
Bonding pads for testing of a semiconductor device Grant 7,259,582 - Ong August 21, 2	2007-08-21
Integrated circuit testing module including data compression App 20070168808 - Ong; Adrian E.	2007-07-19
Shared bond pad for testing a memory within a packaged semiconductor device Grant 7,245,141 - Ong July 17, 2	2007-07-17
Multiple power levels for a chip within a multi-chip semiconductor package Grant 7,240,254 - Ong July 3, 2	2007-07-03
Component testing and recovery App 20070094555 - Ong; Adrian E. ; et al.	2007-04-26
Shared memory bus architecture for system with processor and memory units App 20070013402 - Ong; Adrian E. ; et al.	2007-01-18
System and methods for a high-speed dynamic data bus Grant 7,157,940 - Ong January 2, 2	2007-01-02
Electronic device having an interface supported testing mode App 20060279308 - Ong; Adrian E.	2006-12-14
Chip testing within a multi-chip semiconductor package Grant 7,139,945 - Ong November 21, 2	2006-11-21
Integrated circuit test array including test module App 20060253266 - Ong; Adrian E.	2006-11-09
Monitoring signals between two integrated circuit devices within a single package Grant 7,133,798 - Ong November 7, 2	2006-11-07
Testing of integrated circuit devices Grant 7,103,815 - Ong , et al. September 5, 2	2006-09-05
Shared bond pad for testing a memory within a packaged semiconductor device App 20060152241 - Ong; Adrian E.	2006-07-13
Integrated circuit testing module App 20060150046 - Ong; Adrian E.	2006-07-06
Layout and use of bond pads and probe pads for testing of integrated circuits devices Grant 7,061,263 - Ong June 13, 2	2006-06-13
Set up for a first integrated circuit chip to allow for testing of a co-packaged second integrated circuit chip Grant 7,006,940 - Ong February 28, 2	2006-02-28
High-speed segmented data bus architecture Grant 6,996,652 - Ong February 7, 2	2006-02-07
Bonding pads for testing of a semiconductor device Grant 6,882,171 - Ong April 19, 2	2005-04-19
Entering test mode and accessing of a packaged semiconductor device Grant 6,812,726 - Ong November 2, 2	2004-11-02
Testing of integrated circuit devices Grant 6,754,866 - Ong , et al. June 22, 2	2004-06-22
Chip testing within a multi-chip semiconductor package Grant 6,732,304 - Ong May 4, 2	2004-05-04
Circuit and method for determining the operating point of a semiconductor device Grant 6,693,449 - Gorgen February 17, 2	2004-02-17
Configurable addressing for multiple chips in a package Grant 6,657,914 - Ong , et al. December 2, 2	2003-12-02

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