Imori; Hiromitsu

Patent Applications and Registrations

Patent applications and USPTO patent grants for Imori; Hiromitsu.The latest application filed is for "information processing system with prefetch instructions having indicator bits specifying cache levels for prefetching".

Company Profile

0.8.4

Imori; Hiromitsu - Hadano JP
Imori, Hiromitsu - Hadano-shi JP
Imori; Hiromitsu - Tsukuba JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Processing device with prefetch instructions having indicator bits specifying cache levels for prefetching Grant 7,028,160 - Matsubara , et al. April 11, 2	2006-04-11
Processing device with prefetch instructions having indicator bits specifying cache levels for prefetching Grant 7,028,159 - Matsubara , et al. April 11, 2	2006-04-11
Information processing system with prefetch instructions having indicator bits specifying cache levels for prefetching App 20030208659 - Matsubara, Kenji ; et al.	2003-11-06
Processing device which prefetches instruction having indicator bits specifying a quantity of operand data for prefetching App 20030196045 - Matsubara, Kenji ; et al.	2003-10-16
Information processing system with prefetch instructions having indicator bits specifying a quantity of operand data for prefetching Grant 6,598,127 - Matsubara , et al. July 22, 2	2003-07-22
Processing device which prefetches instructions having indicator bits specifying cache levels for prefetching Grant 6,598,126 - Matsubara , et al. July 22, 2	2003-07-22
Information Processing System With Prefetch Instructions Having Indicator Bits Specifying Cache Levels For Prefetching App 20020083272 - Matsubara, Kenji ; et al.	2002-06-27
Information processing system with prefetch instructions having indicator bits specifying cache levels for prefetching App 20020083273 - Matsubara, Kenji ; et al.	2002-06-27
Information processing system with prefetch instructions having indicator bits specifying cache levels for prefetching Grant 6,381,679 - Matsubara , et al. April 30, 2	2002-04-30
Information processing unit and method for controlling a hierarchical cache utilizing indicator bits to control content of prefetching operations Grant 6,131,145 - Matsubara , et al. October 10, 2	2000-10-10
Data processor with improved loop handling utilizing improved register allocation Grant 5,438,669 - Nakazawa , et al. August 1, 1	1995-08-01

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