loadpatents
name:-0.025141000747681
name:-0.024765014648438
name:-0.0018279552459717
Igarashi; Mutsunori Patent Filings

Igarashi; Mutsunori

Patent Applications and Registrations

Patent applications and USPTO patent grants for Igarashi; Mutsunori.The latest application filed is for "computer implemented design system, a computer implemented design method, a reticle set, and an integrated circuit".

Company Profile
0.20.14
  • Igarashi; Mutsunori - Yokohama JP
  • Igarashi; Mutsunori - Tokyo JP
  • Igarashi; Mutsunori - Yokohama-shi JP
  • Igarashi; Mutsunori - Kanagawa-ken JP
  • Igarashi; Mutsunori - Kanagawa JP
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Computer implemented design system, a computer implemented design method, a reticle set, and an integrated circuit
Grant 7,539,952 - Watanabe , et al. May 26, 2
2009-05-26
Noise suppression circuit, ASIC, navigation apparatus, communication circuit, and communication apparatus having the same
Grant 7,230,554 - Takeuchi , et al. June 12, 2
2007-06-12
Computer implemented design system, a computer implemented design method, a reticle set, and an integrated circuit
App 20070011638 - Watanabe; Atsushi ;   et al.
2007-01-11
Computer implemented design system, a computer implemented design method, a reticle set, and an integrated circuit
Grant 7,127,694 - Watanabe , et al. October 24, 2
2006-10-24
Automated wiring pattern layout method
Grant 7,124,389 - Igarashi , et al. October 17, 2
2006-10-17
Noise suppression circuit, ASIC, navigation apparatus, communication circuit, and communication apparatus having the same
App 20060197695 - Takeuchi; Hideki ;   et al.
2006-09-07
Noise suppression circuit, ASIC, navigation apparatus, communication circuit, and communication apparatus having the same
Grant 7,064,691 - Takeuchi , et al. June 20, 2
2006-06-20
Layout design system, layout design method and layout design program of semiconductor integrated circuit, and method of manufacturing the same
Grant 7,013,444 - Igarashi , et al. March 14, 2
2006-03-14
Computer implemented design system, a computer implemented design method, a reticle set, and an integrated circuit
App 20050166176 - Watanabe, Atsushi ;   et al.
2005-07-28
Method, apparatus and program for designing a semiconductor integrated circuit by adjusting loading of paths
Grant 6,904,572 - Igarashi June 7, 2
2005-06-07
Integrated circuit device, clock layout system, clock layout method, and clock layout program
App 20040237060 - Igarashi, Mutsunori ;   et al.
2004-11-25
Method of automatic layout design for LSI, mask set and semiconductor integrated circuit manufactured by automatic layout design method, and recording medium storing automatic layout design program
Grant 6,813,756 - Igarashi , et al. November 2, 2
2004-11-02
Automated wiring pattern layout method
App 20040210862 - Igarashi, Mutsunori ;   et al.
2004-10-21
Layout design system, layout design method and layout design program of semiconductor integrated circuit, and method of manufacturing the same
App 20040199892 - Igarashi, Mutsunori ;   et al.
2004-10-07
Pattern correction method, apparatus, and program
Grant 6,792,593 - Takashima , et al. September 14, 2
2004-09-14
Automated wiring pattern layout method
Grant 6,779,167 - Igarashi , et al. August 17, 2
2004-08-17
Layout design system, layout design method and layout design program of semiconductor integrated circuit, and method of manufacturing the same
Grant 6,763,508 - Igarashi , et al. July 13, 2
2004-07-13
Semiconductor Integrated Circuit, Supply Method For Supplying Multiple Supply Voltages In Semiconductor Integrated Circuit, And Record Medium For Storing Program Of Supply Method For Supplying Multiple Supply Voltages In Semiconductor Integrated Circuit
Grant 6,683,336 - Igarashi , et al. January 27, 2
2004-01-27
Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method
Grant 6,645,842 - Igarashi , et al. November 11, 2
2003-11-11
Method, apparatus and program for designing a semiconductor integrated circuit
App 20030167451 - Igarashi, Mutsunori
2003-09-04
Method of automatic layout design for LSI, mask set and semiconductor integrated circuit manufactured by automatic layout design method, and recording medium storing automatic layout design program
App 20030079194 - Igarashi, Mutsunori ;   et al.
2003-04-24
Method of automatic layout design for LSI, mask set and semiconductor integrated circuit manufactured by automatic layout design method, and recording medium storing automatic layout design program
Grant 6,546,540 - Igarashi , et al. April 8, 2
2003-04-08
Noise suppression circuit, asic, navigation apparatus, communication circuit, and communication apparatus having the same
App 20030011500 - Takeuchi, Hideki ;   et al.
2003-01-16
Layout design system, layout design method and layout design program of semiconductor integrated circuit, and method of manufacturing the same
App 20030005399 - Igarashi, Mutsunori ;   et al.
2003-01-02
Pattern correction method, apparatus, and program
App 20030005390 - Takashima, Makoto ;   et al.
2003-01-02
Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method
App 20020182844 - Igarashi, Mutsunori ;   et al.
2002-12-05
Automated wiring pattern layout method
App 20020162079 - Igarashi, Mutsunori ;   et al.
2002-10-31
Noise suppression circuit, ASIC, navigation apparatus communication circuit, and communication apparatus having the same
Grant 6,459,331 - Takeuchi , et al. October 1, 2
2002-10-01
Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method
Grant 6,436,804 - Igarashi , et al. August 20, 2
2002-08-20
Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method
App 20010011776 - Igarashi, Mutsunori ;   et al.
2001-08-09
Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method
Grant 6,262,487 - Igarashi , et al. July 17, 2
2001-07-17
Layout method of wiring pattern for semiconductor integrated circuit
Grant 5,801,960 - Takano , et al. September 1, 1
1998-09-01
Method for arranging logical cells in a semiconductor integrated circuit
Grant 5,397,749 - Igarashi March 14, 1
1995-03-14
Arrangement method for logic cells in semiconductor IC device
Grant 5,224,057 - Igarashi , et al. June 29, 1
1993-06-29

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