Iadanza; Joseph A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Iadanza; Joseph A..The latest application filed is for "testing integrated circuit designs containing multiple phase rotators".

Company Profile

1.63.66

Iadanza; Joseph A. - Hinesburg VT
Iadanza; Joseph A - Essex Junction VT
Iadanza; Joseph A. - Essex Junction VT
Iadanza; Joseph A. - US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Testing integrated circuit designs containing multiple phase rotators Grant 11,016,144 - Gerowitz , et al. May 25, 2	2021-05-25
Testing integrated circuit designs containing multiple phase rotators Grant 10,761,136 - Gerowitz , et al. Sep	2020-09-01
Testing Integrated Circuit Designs Containing Multiple Phase Rotators App 20200150175 - GEROWITZ; Robert G. ; et al.	2020-05-14
Testing integrated circuit designs containing multiple phase rotators Grant 10,585,140 - Gerowitz , et al.	2020-03-10
Testing integrated circuit designs containing multiple phase rotators Grant 9,927,489 - Gerowitz , et al. March 27, 2	2018-03-27
Testing Integrated Circuit Designs Containing Multiple Phase Rotators App 20180074121 - GEROWITZ; Robert G. ; et al.	2018-03-15
Testing Integrated Circuit Designs Containing Multiple Phase Rotators App 20180074120 - GEROWITZ; Robert G. ; et al.	2018-03-15
Testing Integrated Circuit Designs Containing Multiple Phase Rotators App 20150198661 - GEROWITZ; Robert G. ; et al.	2015-07-16
Tunable capacitor Grant 9,070,791 - Barrows , et al. June 30, 2	2015-06-30
Real-time adaptive voltage control of logic blocks Grant 8,988,140 - Graf , et al. March 24, 2	2015-03-24
Network reconfiguration in a data converter for improved electrical characteristics Grant 8,978,005 - Iadanza March 10, 2	2015-03-10
Real-time Adaptive Voltage Control Of Logic Blocks App 20150002217 - Graf; Richard S. ; et al.	2015-01-01
Network Reconfiguration In A Data Converter For Improved Electrical Characteristics App 20140365988 - Iadanza; Joseph A.	2014-12-11
Dual-loop voltage regulator architecture with high DC accuracy and fast response time Grant 8,841,893 - Bulzacchelli , et al. September 23, 2	2014-09-23
Resistor-2 resistor (R-2R) digital-to-analog converter with partial resistor network reconfiguration Grant 8,803,722 - Iadanza August 12, 2	2014-08-12
Resistor-2 resistor (R-2R) digital-to-analog converter with resistor network reversal Grant 8,711,022 - Iadanza April 29, 2	2014-04-29
Current leakage in RC ESD clamps Grant 8,643,987 - Chu , et al. February 4, 2	2014-02-04
Resistor-2 Resistor (r-2r) Digital-to-analog Converter With Resistor Network Reversal App 20130335249 - IADANZA; Joseph A.	2013-12-19
Resistor-2 Resistor (r-2r) Digital-to-analog Converter With Partial Resistor Network Reconfiguration App 20130335248 - IADANZA; Joseph A.	2013-12-19
Current Leakage In Rc Esd Clamps App 20130293991 - Chu; Albert M. ; et al.	2013-11-07
Skewed double differential pair circuit for offset cancellation Grant 8,302,037 - Arsovski , et al. October 30, 2	2012-10-30
Dual-loop Voltage Regulator Architecture With High Dc Accuracy And Fast Response Time App 20120153910 - Bulzacchelli; John F. ; et al.	2012-06-21
Hybrid Fast-slow Passgate Control Methods For Voltage Regulators Employing High Speed Comparators App 20120153909 - Bucossi; William L. ; et al.	2012-06-21
Multiple source-single drain field effect semiconductor device and circuit Grant 7,932,552 - Abadeer , et al. April 26, 2	2011-04-26
Structure for intrinsic RC power distribution for noise filtering of analog supplies Grant 7,932,774 - Bonaccio , et al. April 26, 2	2011-04-26
Low voltage head room detection for reliable start-up of self-biased analog circuits Grant 7,932,641 - Hunter , et al. April 26, 2	2011-04-26
Critical path redundant logic for mitigation of hardware across chip variation Grant 7,898,286 - Arsovski , et al. March 1, 2	2011-03-01
Digital to analog converter having fastpaths Grant 7,868,809 - Iadanza , et al. January 11, 2	2011-01-11
Transition balancing for noise reduction/Di/Dt reduction during design, synthesis, and physical design Grant 7,823,107 - Arsovski , et al. October 26, 2	2010-10-26
Tunable capacitor Grant 7,821,053 - Barrows , et al. October 26, 2	2010-10-26
Design structure for multiple source-single drain field effect semiconductor device and circuit Grant 7,814,449 - Abadeer , et al. October 12, 2	2010-10-12
Micro-phase adjusting and micro-phase adjusting mixer circuits designed with standard field effect transistor structures Grant 7,795,940 - Abadeer , et al. September 14, 2	2010-09-14
System, structure and method of providing dynamic optimization of integrated circuits using a non-contact method of selection, and a design structure Grant 7,793,237 - Bonaccio , et al. September 7, 2	2010-09-07
Critical Path Redundant Logic for Mitigation of Hardware Across Chip Variation App 20100201377 - ARSOVSKI; Igor ; et al.	2010-08-12
Design structure for a flexible multimode logic element for use in a configurable mixed-logic signal distribution path Grant 7,770,139 - Arsovski , et al. August 3, 2	2010-08-03
Transceiver for receiving and transmitting data over a network and method for testing the same Grant 7,760,796 - Iadanza July 20, 2	2010-07-20
Intrinsic RC power distribution for noise filtering of analog supplies Grant 7,755,420 - Bonaccio , et al. July 13, 2	2010-07-13
Assigning clock arrival time for noise reduction Grant 7,743,270 - Arsovski , et al. June 22, 2	2010-06-22
Apparatus for improved SRAM device performance through double gate topology Grant 7,729,159 - Braceras , et al. June 1, 2	2010-06-01
Design structures of powering on integrated circuit Grant 7,716,007 - Arsovski , et al. May 11, 2	2010-05-11
Design structures and systems involving digital to analog converters Grant 7,710,302 - Iadanza , et al. May 4, 2	2010-05-04
Design structure to eliminate step response power supply perturbation Grant 7,705,626 - Arsovski , et al. April 27, 2	2010-04-27
Detection method for identifying unintentionally forward-biased diode devices in an integrated circuit device design Grant 7,685,548 - Baizley , et al. March 23, 2	2010-03-23
Micro-phase Adjusting And Micro-phase Adjusting Mixer Circuits Designed With Standard Field Effect Transistor Structures App 20100019816 - Abadeer; Wagdi W. ; et al.	2010-01-28
Transition balancing for noise reduction /Di/Dt reduction during design, synthesis, and physical design Grant 7,643,591 - Arsovski , et al. January 5, 2	2010-01-05
Skewed Double Differential Pair Circuit for Offset Cancelllation App 20090261882 - Arsovski; Igor ; et al.	2009-10-22
Design structure for implementing oxide leakage based voltage divider network for integrated circuit devices Grant 7,579,897 - Goodnow , et al. August 25, 2	2009-08-25
High Speed Resistor-based Digital-to-analog Converter (dac) Architecture App 20090160689 - Iadanza; Joseph A. ; et al.	2009-06-25
Digital to Analog Converter Having Fastpaths App 20090160691 - Iadanza; Joseph A. ; et al.	2009-06-25
System, Structure and Method of Providing Dynamic Optimization of Integrated Circuits Using a Non-Contact Method of Selection, and a Design Structure App 20090152543 - Bonaccio; Anthony R. ; et al.	2009-06-18
Tunable Capacitor App 20090108320 - Barrows; Corey K. ; et al.	2009-04-30
Design Structure for a Flexible Multimode Logic Element For Use In A Configurable Mixed-Logic Signal Distribution Path App 20090108869 - Arsovski; Igor ; et al.	2009-04-30
Dual Gate Fet Structures For Flexible Gate Array Design Methodologies App 20090101940 - Barrows; Corey K. ; et al.	2009-04-23
Shifting Inactive Clock Edge For Noise Reduction App 20090102529 - Arsovski; Igor ; et al.	2009-04-23
Multiple Source-Single Drain Field Effect Semiconductor Device and Circuit App 20090106707 - Abadeer; Wagdi W. ; et al.	2009-04-23
Transition Balancing For Noise Reduction/Di/Dt Reduction During Design, Synthesis, and Physical Design App 20090106724 - Arsovski; Igor ; et al.	2009-04-23
Detection Method for Identifying Unintentionally Forward-Biased Diode Devices in an Integrated Circuit Device Design App 20090089724 - Baizley; Arnold E. ; et al.	2009-04-02
Device and method to eliminate step response power supply perturbation Grant 7,511,528 - Arsovski , et al. March 31, 2	2009-03-31
Clock distribution network, structure, and method for providing balanced loading in integrated circuit clock trees Grant 7,511,548 - Bueti , et al. March 31, 2	2009-03-31
Intrinsic Rc Power Distribution For Noise Filtering Of Analog Supplies App 20090051420 - Bonaccio; Anthony R. ; et al.	2009-02-26
Micro-phase Adjusting And Micro-phase Adjusting Mixer Circuits Designed With Standard Field Effect Transistor Structures App 20090033389 - Abadeer; Wagdi W. ; et al.	2009-02-05
Multiple Source-single Drain Field Effect Semiconductor Device And Circuit App 20090033395 - Abadeer; Wagdi W. ; et al.	2009-02-05
Design structures, method and systems of powering on integrated circuit Grant 7,483,806 - Arsovski , et al. January 27, 2	2009-01-27
Structures Of Powering On Integrated Circuit App 20090024972 - Arsovski; Igor ; et al.	2009-01-22
Design Structures, Method And Systems Of Powering On Integrated Circuit App 20090021085 - Arsovski; Igor ; et al.	2009-01-22
Clock distribution network, structure, and method for providing balanced loading in integrated circuit clock trees Grant 7,479,819 - Bueti , et al. January 20, 2	2009-01-20
Transceiver For Receiving And Transmitting Data Over A Network And Method For Testing The Same App 20090003419 - Iadanza; Joseph A.	2009-01-01
Low Voltage Head Room Detection For Reliable Start-Up Of Self-Biased Analog Circuits App 20080304192 - Hunter; Bradford L. ; et al.	2008-12-11
Method and apparatus for storing circuit calibration information Grant 7,454,305 - Bonaccio , et al. November 18, 2	2008-11-18
Intrinsic RC power distribution for noise filtering of analog supplies Grant 7,449,942 - Bonaccio , et al. November 11, 2	2008-11-11
Apparatus For Improved Sram Device Performance Through Double Gate Topology App 20080273373 - Braceras; George M. ; et al.	2008-11-06
Design Structure For Improved Sram Device Performance Through Double Gate Topology App 20080273366 - Braceras; George M. ; et al.	2008-11-06
System And Method For Balancing Delay Of Signal Communication Paths Through Well Voltage Adjustment App 20080240222 - Cranford; Hayden C. ; et al.	2008-10-02
Structure For Intrinsic Rc Power Distribution For Noise Filtering Of Analog Supplies App 20080244479 - BONACCIO; Anthony R. ; et al.	2008-10-02
Design structure for a flexible multimode logic element for use in a configurable mixed-logic signal distribution path Grant 7,429,877 - Arsovski , et al. September 30, 2	2008-09-30
Design Structure for a Clock Distribution Network, Structure, and Method for Providing Balanced Loading in Integrated Circuit Clock Trees App 20080229265 - Bueti; Serafino ; et al.	2008-09-18
Design Structure for a Clock Distribution Network, Structure, and Method for Providing Balanced Loading in Integrated Circuit Clock Trees App 20080229266 - Bueti; Serafino ; et al.	2008-09-18
Flexible Multimode Logic Element For Use In A Configurable Mixed-logic Signal Distribution Path App 20080186051 - Arsovski; Igor ; et al.	2008-08-07
Design Structure For A Flexible Multimode Logic Element For Use In A Configurable Mixed-logic Signal Distribution Path App 20080186054 - Arsovski; Igor ; et al.	2008-08-07
Apparatus and method for improved SRAM device performance through double gate topology Grant 7,408,800 - Braceras , et al. August 5, 2	2008-08-05
Flexible multimode logic element for use in a configurable mixed-logic signal distribution path Grant 7,403,039 - Arsovski , et al. July 22, 2	2008-07-22
System and method for balancing delay of signal communication paths through well voltage adjustment Grant 7,404,114 - Cranford, Jr. , et al. July 22, 2	2008-07-22
Design Structure For Implementing Oxide Leakage Based Voltage Divider Network For Integrated Circuit Devices App 20080157858 - Goodnow; Kenneth J. ; et al.	2008-07-03
Clock Distribution Network, Structure, And Method For Providing Balanced Loading In Integrated Circuit Clock Trees App 20080148204 - Bueti; Serafino ; et al.	2008-06-19
Clock Distribution Network, Structure, And Method For Providing Balanced Loading In Integrated Circuit Clock Trees App 20080143416 - Bueti; Serafino ; et al.	2008-06-19
Tunable Capacitor App 20080111176 - Barrows; Corey K. ; et al.	2008-05-15
Flexible multimode logic element for use in a configurable mixed-logic signal distribution path Grant 7,362,138 - Arsovski , et al. April 22, 2	2008-04-22
Assigning Clock Arrival Time For Noise Reduction App 20080065923 - Arsovski; Igor ; et al.	2008-03-13
TRANSITION BALANCING FOR NOISE REDUCTION /di/dt REDUCTION DURING DESIGN, SYNTHESIS, AND PHYSICAL DESIGN App 20080043890 - Arsovski; Igor ; et al.	2008-02-21
Shifting Inactive Clock Edge For Noise Reduction App 20080046772 - Arsovski; Igor ; et al.	2008-02-21
Design Structure To Eliminate Step Response Power Supply Perturbation App 20080030254 - Arsovski; Igor ; et al.	2008-02-07
Device And Method To Eliminate Step Response Power Supply Perturbation App 20080030223 - Arsovski; Igor ; et al.	2008-02-07
Transceiver for receiving and transmitting data over a network and method for testing the same Grant 7,313,178 - Iadanza December 25, 2	2007-12-25
Structure and method for implementing oxide leakage based voltage divider network for integrated circuit devices Grant 7,307,467 - Goodnow , et al. December 11, 2	2007-12-11
Structure And Method For Implementing Oxide Leakage Based Voltage Divider Network For Integrated Circuit Devices App 20070278582 - Goodnow; Kenneth J. ; et al.	2007-12-06
Structure And Method For Implementing Oxide Leakage Based Voltage Divider Network For Integrated Circuit Devices App 20070252641 - Goodnow; Kenneth J. ; et al.	2007-11-01
Method and Apparatus for Converting Globally Clock-Gated Circuits to Locally Clock-Gated Circuits App 20070220468 - Haar; Allen P. ; et al.	2007-09-20
Structure and method for providing gate leakage isolation locally within analog circuits Grant 7,268,632 - Bonaccio , et al. September 11, 2	2007-09-11
Intrinsic Rc Power Distribution For Noise Filtering Of Analog Supplies App 20070200744 - Bonaccio; Anthony R. ; et al.	2007-08-30
Method and apparatus for converting globally clock-gated circuits to locally clock-gated circuits Grant 7,257,788 - Haar , et al. August 14, 2	2007-08-14
Method And Apparatus For Storing Circuit Calibration Information App 20070115019 - Bonaccio; Anthony R. ; et al.	2007-05-24
Method and apparatus for reducing noise in a dynamic manner Grant 7,218,135 - Arsovski , et al. May 15, 2	2007-05-15
Structure And Method For Providing Gate Leakage Isolation Locally Within Analog Circuits App 20070075789 - Bonaccio; Anthony R. ; et al.	2007-04-05
System And Method For Balancing Delay Of Signal Communication Paths Through Well Voltage Adjustment App 20060181323 - Cranford; Hayden C. Jr. ; et al.	2006-08-17
Method for optimal use of direct fit and interpolated models in schematic custom design of electrical circuits Grant 7,089,512 - Iadanza , et al. August 8, 2	2006-08-08
Method And Apparatus For Converting Globally Clock-gated Circuits To Locally Clock-gated Circuits App 20060101362 - Haar; Allen P. ; et al.	2006-05-11
Method for designing an integrated circuit having multiple voltage domains Grant 7,000,214 - Iadanza , et al. February 14, 2	2006-02-14
Method of connecting core I/O pins to backside chip I/O pads Grant 6,960,837 - Iadanza November 1, 2	2005-11-01
Method For Optimal Use Of Direct Fit And Interpolated Models In Schematic Custom Design Of Electrical Circuits App 20050204318 - Iadanza, Joseph A. ; et al.	2005-09-15
Method and circuit for testing a regulated power supply in an integrated circuit Grant 6,927,590 - Iadanza August 9, 2	2005-08-09
Method For Designing An Integrated Circuit Having Multiple Voltage Domains App 20050108667 - Iadanza, Joseph A. ; et al.	2005-05-19
System and method for control parameter re-centering in a controlled phase lock loop system Grant 6,882,230 - Iadanza , et al. April 19, 2	2005-04-19
Method And Circuit For Testing A Regulated Power Supply In An Integrated Circuit App 20050040841 - Iadanza, Joseph A.	2005-02-24
System And Method For Control Parameter Re-centering In A Controlled Phase Lock Loop System App 20040263259 - Iadanza, Joseph A. ; et al.	2004-12-30
Method of automatic latch insertion for testing application specific integrated circuits Grant 6,636,995 - Dean , et al. October 21, 2	2003-10-21
Transceiver for receiving and transmitting data over a network and method for testing the same App 20030193996 - Iadanza, Joseph A.	2003-10-16
Method of connecting core I/O pins to backside chip I/O pads App 20030160293 - Iadanza, Joseph A.	2003-08-28
Low Skew, Power Sequence Independent Cmos Receiver Device App 20030001642 - Dale, Bret R. ; et al.	2003-01-02
System and method for AC performance tuning by thereshold voltage shifting in tubbed semiconductor technology Grant 6,487,701 - Dean , et al. November 26, 2	2002-11-26
Cross-coupled bitline segments for generalized data propagation Grant 5,745,422 - Iadanza April 28, 1	1998-04-28
Programmable array interconnect network Grant 5,631,578 - Clinton , et al. May 20, 1	1997-05-20