Iacoponi; John A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Iacoponi; John A..The latest application filed is for "semiconductor device configured for avoiding electrical shorting".

Company Profile

0.30.8

Iacoponi; John A. - Saratoga Springs NY
Iacoponi; John A. - Wappingers Falls NY
Iacoponi; John A. - Austin TX
Iacoponi; John A. - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor device configured for avoiding electrical shorting Grant 10,050,118 - Xie , et al. August 14, 2	2018-08-14
Semiconductor Device Configured For Avoiding Electrical Shorting App 20150318345 - XIE; Ruilong ; et al.	2015-11-05
Methods of forming semiconductor device with self-aligned contact elements and the resulting devices Grant 8,946,075 - Cai , et al. February 3, 2	2015-02-03
Methods of forming semiconductor device with self-aligned contact elements and the resulting devices Grant 8,940,633 - Cai , et al. January 27, 2	2015-01-27
Methods Of Forming Semiconductor Device With Self-aligned Contact Elements And The Resulting Devices App 20140252424 - Cai; Xiuyu ; et al.	2014-09-11
Methods Of Forming Semiconductor Device With Self-aligned Contact Elements And The Resulting Devices App 20140252425 - Cai; Xiuyu ; et al.	2014-09-11
Method for depositing a conductive capping layer on metal lines Grant 8,592,312 - Ryan , et al. November 26, 2	2013-11-26
Methods For Forming An Integrated Circuit With Straightened Recess Profile App 20130309868 - Cai; Xiuyu ; et al.	2013-11-21
Enhancing structural integrity and defining critical dimensions of metallization systems of semiconductor devices by using ALD techniques Grant 8,105,943 - Streck , et al. January 31, 2	2012-01-31
Enhancing Structural Integrity And Defining Critical Dimensions Of Metallization Systems Of Semiconductor Devices By Using Ald Techniques App 20100025855 - Streck; Christof ; et al.	2010-02-04
Method of forming semiconductor devices by microwave curing of low-k dielectric films Grant 7,557,035 - Ryan , et al. July 7, 2	2009-07-07
Mos Transistors For Thin Soi Integration And Methods For Fabricating The Same App 20090045458 - IACOPONI; John A. ; et al.	2009-02-19
Method for depositing a conductive capping layer on metal lines App 20080305617 - Ryan; E. Todd ; et al.	2008-12-11
Method and apparatus for detecting the endpoint of a chemical-mechanical polishing operation using optical techniques Grant 6,809,032 - Mauersberger , et al. October 26, 2	2004-10-26
Method and apparatus for forming an under bump metallurgy layer Grant 6,649,533 - Iacoponi November 18, 2	2003-11-18
Method for forming openings for conductive interconnects Grant 6,555,479 - Hause , et al. April 29, 2	2003-04-29
Test structure for providing depth of polish feedback Grant 6,514,858 - Hause , et al. February 4, 2	2003-02-04
Method for forming copper interconnects Grant 6,489,240 - Iacoponi , et al. December 3, 2	2002-12-03
Variable grain size in conductors for semiconductor vias and trenches Grant 6,489,683 - Lopatin , et al. December 3, 2	2002-12-03
Backside contact for integrated circuit and method of forming same Grant 6,468,889 - Iacoponi , et al. October 22, 2	2002-10-22
Contact each methodology and integration scheme Grant 6,413,846 - Besser , et al. July 2, 2	2002-07-02
Alloy barrier layers for semiconductors Grant 6,362,526 - Pramanick , et al. March 26, 2	2002-03-26
Semiconductor metalization barrier and manufacturing method therefor Grant 6,320,263 - Lopatin , et al. November 20, 2	2001-11-20
Method for forming semiconductor seed layers by high bias deposition Grant 6,261,946 - Iacoponi , et al. July 17, 2	2001-07-17
Dual barrier and conductor deposition in a dual damascene process for semiconductors Grant 6,239,021 - Pramanick , et al. May 29, 2	2001-05-29
Method for forming semiconductor seed layers by inert gas sputter etching Grant 6,228,754 - Iacoponi , et al. May 8, 2	2001-05-08
Multi-stage method for forming optimized semiconductor seed layers Grant 6,187,670 - Brown , et al. February 13, 2	2001-02-13
Integration of low-K SiOF as inter-layer dielectric for AL-gapfill application Grant 6,166,427 - Huang , et al. December 26, 2	2000-12-26
Dual barrier and conductor deposition in a dual damascene process for semiconductors Grant 6,147,404 - Pramanick , et al. November 14, 2	2000-11-14
Method for forming in-situ implanted semiconductor barrier layers Grant 6,146,993 - Brown , et al. November 14, 2	2000-11-14
Method for implanting semiconductor conductive layers Grant 6,117,770 - Pramanick , et al. September 12, 2	2000-09-12
Electroplating uniformity by diffuser design Grant 6,103,085 - Woo , et al. August 15, 2	2000-08-15
Semiconductor interconnect interface processing by high pressure deposition Grant 6,080,669 - Iacoponi , et al. June 27, 2	2000-06-27
Metalorganic decomposition deposition of thin conductive films on integrated circuits using reducing ambient Grant 6,048,790 - Iacoponi , et al. April 11, 2	2000-04-11
Borderless vias with CVD barrier layer Grant 5,969,425 - Chen , et al. October 19, 1	1999-10-19
Deposition of a conductor in a via hole or trench Grant 5,918,149 - Besser , et al. June 29, 1	1999-06-29

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