loadpatents
name:-0.0056648254394531
name:-0.017910957336426
name:-0.0006568431854248
Iachetta, Jr.; Richard Nicholas Patent Filings

Iachetta, Jr.; Richard Nicholas

Patent Applications and Registrations

Patent applications and USPTO patent grants for Iachetta, Jr.; Richard Nicholas.The latest application filed is for "target directed completion for bus transactions".

Company Profile
0.9.1
  • Iachetta, Jr.; Richard Nicholas - Pflugerville TX
  • Iachetta Jr., Richard Nicholas - Pfluqerville TX
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Method and apparatus for implementing power-saving sleep mode in design with multiple clock domains
Grant 7,080,269 - Baumgartner , et al. July 18, 2
2006-07-18
System and method for providing improved bus utilization via target directed completion
Grant 6,973,520 - Drerup , et al. December 6, 2
2005-12-06
Method and apparatus for preserving the contents of synchronous DRAM through system reset
Grant 6,829,677 - Attaway , et al. December 7, 2
2004-12-07
Method and apparatus for passing messages through a bus-to-bus bridge while maintaining ordering
Grant 6,801,977 - Drerup , et al. October 5, 2
2004-10-05
Target directed completion for bus transactions
App 20020078282 - Drerup, Bernard Charles ;   et al.
2002-06-20
Method and system for avoiding data loss due to cancelled transactions within a non-uniform memory access system
Grant 6,192,452 - Bannister , et al. February 20, 2
2001-02-20
Queue having distributed multiplexing logic
Grant 6,178,472 - Carpenter , et al. January 23, 2
2001-01-23
Non-uniform memory access (NUMA) data processing system that speculatively issues requests on a node interconnect
Grant 6,081,874 - Carpenter , et al. June 27, 2
2000-06-27
Apparatus and method for protecting system serial number while allowing motherboard replacement
Grant 5,864,664 - Capps, Jr. , et al. January 26, 1
1999-01-26
Method and apparatus for allowing multi-speed synchronous communications between a processor and both slow and fast computing devices
Grant 5,727,171 - Iachetta, Jr. March 10, 1
1998-03-10

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