Hwang; Chorng-Lii

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hwang; Chorng-Lii.The latest application filed is for "destructive-read random access memory system buffered with destructive-read memory cache".

Company Profile

0.10.7

Hwang; Chorng-Lii - Wappingers Falls NY
Hwang; Chorng-Lii - Wappinger Falls NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Destructive-read random access memory system buffered with destructive-read memory cache Grant 7,203,794 - Ji , et al. April 10, 2	2007-04-10
System and method for disconnecting a portion of an integrated circuit Grant 7,057,866 - Hsu , et al. June 6, 2	2006-06-06
Destructive-read Random Access Memory System Buffered With Destructive-read Memory Cache App 20050226083 - Ji, Brian L. ; et al.	2005-10-13
Destructive-read random access memory system buffered with destructive-read memory cache Grant 6,948,028 - Ji , et al. September 20, 2	2005-09-20
Destructive-read Random Access Memory System Buffered With Destructive-read Memory Cache App 20040221097 - Ji, Brian L. ; et al.	2004-11-04
Destructive-read random access memory system buffered with destructive-read memory cache Grant 6,801,980 - Ji , et al. October 5, 2	2004-10-05
Column redundancy system and method for a micro-cell embedded DRAM (e-DRAM) architecture Grant 6,674,676 - Hsu , et al. January 6, 2	2004-01-06
Column redundancy system and method for a micro-cell embedded DRAM (e-DRAM) architecture Grant 6,674,673 - Hsu , et al. January 6, 2	2004-01-06
Destructive-read random access memory system buffered with destructive-read memory cache App 20030204667 - Ji, Brian L. ; et al.	2003-10-30
Pad system for an integrated circuit or device Grant 6,621,294 - Hsu , et al. September 16, 2	2003-09-16
Pad System For An Integrated Circuit Or Device App 20030122576 - Hsu, Louis L. ; et al.	2003-07-03
System and method for disconnecting a portion of an integrated circuit App 20030034825 - Hsu, Louis L. ; et al.	2003-02-20
Method and system for background ECC scrubbing for a memory array App 20030009721 - Hsu, Louis L. ; et al.	2003-01-09
Method And Apparatus For Resist Planarization App 20010006761 - GOLZ, JOHN ; et al.	2001-07-05
Damascene process for forming ferroelectric capacitors Grant 6,238,963 - Chen , et al. May 29, 2	2001-05-29
Structure and method for reliability stressing of dielectrics Grant 5,898,706 - Dufresne , et al. April 27, 1	1999-04-27
Microplanarization of rough electrodes by thin amorphous layers Grant 5,587,614 - Hwang , et al. December 24, 1	1996-12-24

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