Hutton; Michael D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hutton; Michael D..The latest application filed is for "clock synthesis for frequency scaling in programmable logic designs".

Company Profile

4.81.22

Hutton; Michael D. - Palo Alto CA
Hutton; Michael D. - Mountain View CA
Hutton; Michael D. - San Jose CA
Hutton; Michael D. - San Francisco CA
Hutton; Michael D - Mountain View CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Hybrid programmable many-core device with on-chip interconnect Grant 11,256,656 - Hutton , et al. February 22, 2	2022-02-22
Clock Synthesis For Frequency Scaling In Programmable Logic Designs App 20220014204 - Hutton; Michael D. ; et al.	2022-01-13
Clock synthesis for frequency scaling in programmable logic designs Grant 11,177,811 - Hutton , et al. November 16, 2	2021-11-16
Hybrid Programmable Many-core Device With On-chip Interconnect App 20200257651 - A1	2020-08-13
Hybrid programmable many-core device with on-chip interconnect Grant 10,635,631 - Hutton , et al.	2020-04-28
Hybrid Programmable Many-core Device With On-chip Interconnect App 20190121783 - Hutton; Michael D. ; et al.	2019-04-25
Clock Synthesis For Frequency Scaling In Programmable Logic Designs App 20190097637 - Hutton; Michael D. ; et al.	2019-03-28
Hybrid programmable many-core device with on-chip interconnect Grant 10,127,190 - Hutton , et al. November 13, 2	2018-11-13
Configurable storage circuits with embedded processing and control circuitry Grant 9,983,990 - Hutton , et al. May 29, 2	2018-05-29
Hybrid Programmable Many-core Device With On-chip Interconnect App 20180089139 - Hutton; Michael D. ; et al.	2018-03-29
Hybrid programmable many-core device with on-chip interconnect Grant 9,830,300 - Hutton , et al. November 28, 2	2017-11-28
Field programmable gate array with integrated application specific integrated circuit fabric Grant 9,705,506 - Hutton , et al. July 11, 2	2017-07-11
Configurable register circuitry for error detection and recovery Grant 9,583,218 - Hutton , et al. February 28, 2	2017-02-28
Hybrid Programmable Many-core Device With On-chip Interconnect App 20170024355 - Hutton; Michael D. ; et al.	2017-01-26
Mapping network applications to a hybrid programmable many-core device Grant 9,471,388 - Hutton , et al. October 18, 2	2016-10-18
Hybrid programmable many-core device with on-chip interconnect Grant 9,471,537 - Hutton , et al. October 18, 2	2016-10-18
Configurable hybrid adder circuitry Grant 9,292,474 - Pistorius , et al. March 22, 2	2016-03-22
Error resilient packaged components Grant 9,294,092 - Hutton March 22, 2	2016-03-22
Methods and tools for designing integrated circuits with auto-pipelining capabilities Grant 9,251,300 - Hutton , et al. February 2, 2	2016-02-02
Memory blocks with shared address bus circuitry Grant 9,178,513 - Hutton , et al. November 3, 2	2015-11-03
Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers Grant 9,172,378 - Hutton , et al. October 27, 2	2015-10-27
Apparatus for field-programmable gate array with configurable architecture and associated methods Grant 9,165,931 - Schmit , et al. October 20, 2	2015-10-20
Methods and apparatus for building bus interconnection networks using programmable interconnection resources Grant 9,166,599 - Hutton October 20, 2	2015-10-20
Register retiming technique Grant 9,053,274 - van Antwerpen , et al. June 9, 2	2015-06-09
Methods And Tools For Designing Integrated Circuits With Auto-pipelining Capabilities App 20150121319 - Hutton; Michael D. ; et al.	2015-04-30
Method and apparatus for implementing a field programmable gate array architecture with programmable clock skew Grant 8,997,029 - Hutton , et al. March 31, 2	2015-03-31
Error Resilient Packaged Components App 20150028918 - Hutton; Michael D.	2015-01-29
Integrated circuits with logic regions having input and output bypass paths for accessing registers Grant 8,860,458 - Hutton October 14, 2	2014-10-14
Integrated circuits with interconnect selection circuitry Grant 8,854,080 - Hutton , et al. October 7, 2	2014-10-07
Hybrid Programmable Many-Core Device with On-Chip Interconnect App 20140281379 - Hutton; Michael D. ; et al.	2014-09-18
Mapping Network Applications to a Hybrid Programmable Many-Core Device App 20140282560 - Hutton; Michael D. ; et al.	2014-09-18
Register retiming technique Grant 8,806,399 - van Antwerpen , et al. August 12, 2	2014-08-12
Methods And Apparatus For Building Bus Interconnection Networks Using Programmable Interconnection Resources App 20140111247 - Hutton; Michael D.	2014-04-24
Methods and apparatus for building bus interconnection networks using programmable interconnection resources Grant 8,704,548 - Hutton April 22, 2	2014-04-22
Method and apparatus for implementing a field programmable gate array clock skew Grant 8,640,067 - Hutton , et al. January 28, 2	2014-01-28
Integrated Circuits With Logic Regions Having Input And Output Bypass Paths For Accessing Registers App 20140021981 - Hutton; Michael D.	2014-01-23
Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers Grant 8,601,424 - Hutton , et al. December 3, 2	2013-12-03
Integrated circuits with interconnect selection circuitry Grant 8,542,032 - Hutton , et al. September 24, 2	2013-09-24
Integrated circuits with shared interconnect buses Grant 8,519,740 - Hutton , et al. August 27, 2	2013-08-27
Configurable hybrid adder circuitry Grant 8,521,801 - Pistorius , et al. August 27, 2	2013-08-27
Integrated Circuits With Shared Interconnect Buses App 20130176052 - Hutton; Michael D. ; et al.	2013-07-11
Register retiming technique Grant 8,402,408 - van Antwerpen , et al. March 19, 2	2013-03-19
Using a timing exception to postpone retiming Grant 8,381,142 - Hutton February 19, 2	2013-02-19
Field Programmable Gate Array With Integrated Application Specific Integrated Circuit Fabric App 20130009666 - Hutton; Michael D. ; et al.	2013-01-10
Field programmable gate array with integrated application specific integrated circuit fabric Grant 8,314,636 - Hutton , et al. November 20, 2	2012-11-20
Method and apparatus for performing parallel slack computation within a shared netlist region Grant 8,185,854 - Hutton , et al. May 22, 2	2012-05-22
Tracing and reporting registers removed during synthesis Grant 8,166,427 - Pathak , et al. April 24, 2	2012-04-24
Early timing estimation of timing statistical properties of placement Grant 8,112,728 - Hutton , et al. February 7, 2	2012-02-07
Register retiming technique Grant 8,108,812 - van Antwerpen , et al. January 31, 2	2012-01-31
Programmable logic device architecture with the ability to combine adjacent logic elements for the purpose of performing high order logic functions Grant 8,072,238 - Hutton December 6, 2	2011-12-06
Timing control in a specialized processing block Grant 8,020,027 - Hutton September 13, 2	2011-09-13
Circuit type pragma for computer aided design tools Grant 8,001,499 - Baeckler , et al. August 16, 2	2011-08-16
Heterogeneous labs Grant 7,902,864 - Hutton , et al. March 8, 2	2011-03-08
Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers Grant 7,890,910 - Hutton , et al. February 15, 2	2011-02-15
User-accessible freeze-logic for dynamic power reduction and associated methods Grant 7,839,165 - Hutton , et al. November 23, 2	2010-11-23
Time-multiplexed routing for reducing pipelining registers Grant 7,827,433 - Hutton November 2, 2	2010-11-02
Method and apparatus for implementing a field programmable gate array architecture with programmable clock skew Grant 7,818,705 - Hutton , et al. October 19, 2	2010-10-19
Programmable logic device architecture with the ability to combine adjacent logic elements for the purpose of performing high order logic functions Grant 7,812,635 - Hutton October 12, 2	2010-10-12
Dedicated function block interfacing with general purpose function blocks on integrated circuits Grant 7,804,325 - Pistorius , et al. September 28, 2	2010-09-28
Performance visualization system Grant 7,784,008 - Hutton , et al. August 24, 2	2010-08-24
Field Programmable Gate Array With Integrated Application Specific Integrated Circuit Fabric App 20100207659 - Hutton; Michael D. ; et al.	2010-08-19
Method and apparatus for PLD having shared storage elements Grant 7,733,124 - Duwel , et al. June 8, 2	2010-06-08
Field programmable gate array with integrated application specific integrated circuit fabric Grant 7,724,032 - Hutton , et al. May 25, 2	2010-05-25
Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers Grant 7,705,628 - Hutton , et al. April 27, 2	2010-04-27
Register retiming technique Grant 7,689,955 - van Antwerpen , et al. March 30, 2	2010-03-30
Programmable logic device having complex logic blocks with improved logic cell functionality Grant 7,675,319 - Hutton March 9, 2	2010-03-09
User-Accessible Freeze-Logic for Dynamic Power Reduction and Associated Methods App 20100026340 - Hutton; Michael D. ; et al.	2010-02-04
Configurable Hybrid Adder Circuitry App 20090271465 - Pistorius; Erhard Joachim ; et al.	2009-10-29
User-accessible freeze-logic for dynamic power reduction and associated methods Grant 7,605,603 - Hutton , et al. October 20, 2	2009-10-20
Techniques for using edge masks to perform timing analysis Grant 7,607,118 - Hutton October 20, 2	2009-10-20
Programmable logic device with configurable override of region-wide signals Grant 7,579,866 - Hutton , et al. August 25, 2	2009-08-25
Early timing estimation of timing statistical properties of placement Grant 7,577,929 - Hutton , et al. August 18, 2	2009-08-18
Clock distribution for specialized processing block in programmable logic device Grant 7,545,196 - Hutton , et al. June 9, 2	2009-06-09
Field programmable gate array with integrated application specific integrated circuit fabric App 20090051387 - Hutton; Michael D. ; et al.	2009-02-26
Timing variation aware compilation Grant 7,469,394 - Hutton , et al. December 23, 2	2008-12-23
Programmable Logic Device Having Complex Logic Blocks With Improved Logic Cell Functionality App 20080290898 - HUTTON; Michael D.	2008-11-27
Method and apparatus for implementing additional registers in field programmable gate arrays to reduce design size Grant 7,420,390 - Hutton , et al. September 2, 2	2008-09-02
Programmable logic device having complex logic blocks with improved logic cell functionality Grant 7,394,287 - Hutton July 1, 2	2008-07-01
Organizations of logic modules in programmable logic devices Grant 7,368,944 - Hutton , et al. May 6, 2	2008-05-06
Dedicated resource interconnects Grant 7,368,942 - Hutton , et al. May 6, 2	2008-05-06
Physical resynthesis of a logic design Grant 7,337,100 - Hutton , et al. February 26, 2	2008-02-26
Area efficient fractureable logic elements Grant 7,330,052 - Kaptanoglu , et al. February 12, 2	2008-02-12
Programmable routing structures providing shorter timing delays for input/output signals Grant 7,312,633 - Hutton , et al. December 25, 2	2007-12-25
Area efficient fractureable logic elements App 20070063732 - Kaptanoglu; Sinan ; et al.	2007-03-22
Organizations of logic modules in programmable logic devices Grant 7,176,718 - Hutton , et al. February 13, 2	2007-02-13
Programmable routing structures providing shorter timing delays for input/output signals Grant 7,135,888 - Hutton , et al. November 14, 2	2006-11-14
Method for adaptive critical path delay estimation during timing-driven placement for hierarchical programmable logic devices Grant 7,133,819 - Hutton November 7, 2	2006-11-07
Register retiming technique Grant 7,120,883 - van Antwerpen , et al. October 10, 2	2006-10-10
Techniques for using edge masks to perform timing analysis Grant 7,093,219 - Hutton August 15, 2	2006-08-15
Time-multiplexed routing in a programmable logic device architecture Grant 6,977,520 - Hutton , et al. December 20, 2	2005-12-20
Programmable logic devices with bidirect ional cascades Grant 6,747,480 - Kaptanoglu , et al. June 8, 2	2004-06-08

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