Patent | Date |
---|
Circuit Logic Embedded Within Ic Protective Layer App 20090020313 - LEDUC; Yves ;   et al. | 2009-01-22 |
Semiconductor device with an analog capacitor Grant 7,279,738 - Khan , et al. October 9, 2 | 2007-10-09 |
System and method for forming a semiconductor with an analog capacitor using fewer structure steps Grant 6,979,615 - Khan , et al. December 27, 2 | 2005-12-27 |
System and method for forming a semiconductor with an analog capacitor using fewer structure steps App 20050221595 - Khan, Imran M. ;   et al. | 2005-10-06 |
Method of integrating a thin film resistor in a multi-level metal tungsten-plug interconnect Grant 6,737,326 - Steinmann , et al. May 18, 2 | 2004-05-18 |
System and method for forming a semiconductor with an analog capacitor using fewer structure steps App 20040053455 - Khan, Imran M. ;   et al. | 2004-03-18 |
Innovative method to build a high precision analog capacitor with low voltage coefficient and hysteresis Grant 6,706,635 - Khan , et al. March 16, 2 | 2004-03-16 |
Integrated circuit with bonding layer over active circuitry Grant 6,683,380 - Efland , et al. January 27, 2 | 2004-01-27 |
Innovative Method To Build A High Precision Analog Capacitor With Low Voltage Coefficient And Hysteresis App 20030228764 - Khan, Imran M. ;   et al. | 2003-12-11 |
Integrated circuit with bonding layer over active circuitry App 20030036256 - Efland, Taylor R. ;   et al. | 2003-02-20 |
Integrated circuit capacitor and method Grant 6,432,791 - Hutter , et al. August 13, 2 | 2002-08-13 |
LDMOS power device with oversized dwell Grant 6,424,005 - Tsai , et al. July 23, 2 | 2002-07-23 |
Method of integrating a thin film resistor in a multi-level metal tungsten-plug interconnect App 20010049199 - Steinmann, Philipp ;   et al. | 2001-12-06 |
Transistor with increased operating voltage and method of fabrication Grant 6,153,451 - Hutter , et al. November 28, 2 | 2000-11-28 |
Low voltage DMOS transistor Grant 5,825,065 - Corsi , et al. October 20, 1 | 1998-10-20 |
DMOS transistor with low on-resistance and method of fabrication Grant 5,719,421 - Hutter , et al. February 17, 1 | 1998-02-17 |
Method for making an isolated vertical transistor Grant 5,702,959 - Hutter , et al. December 30, 1 | 1997-12-30 |
High voltage Shottky diode Grant 5,614,755 - Hutter , et al. March 25, 1 | 1997-03-25 |
Method for making an EEPROM with thermal oxide isolated floating gate Grant 5,576,233 - Hutter , et al. November 19, 1 | 1996-11-19 |
Semiconductor device having polysilicon resistor with low temperature coefficient Grant 5,554,873 - Erdeljac , et al. September 10, 1 | 1996-09-10 |
Method of fabricating semiconductor device having polysilicon resistor with low temperature coefficient Grant 5,489,547 - Erdeljac , et al. February 6, 1 | 1996-02-06 |
Method of fabricating semiconductor device having high-and low-voltage MOS transistors Grant 5,472,887 - Hutter , et al. December 5, 1 | 1995-12-05 |
Semiconductor process for manufacturing semiconductor devices with increased operating voltages Grant 5,330,922 - Erdeljac , et al. July 19, 1 | 1994-07-19 |
Vertical DMOS transistor built in an n-well MOS-based BiCMOS process Grant 5,317,180 - Hutter , et al. May 31, 1 | 1994-05-31 |
Vertical DMOS transistor structure built in an N-well CMOS-based BiCMOS process and method of fabrication Grant 5,171,699 - Hutter , et al. December 15, 1 | 1992-12-15 |
High voltage merged bipolar/CMOS technology Grant 4,994,887 - Hutter , et al. February 19, 1 | 1991-02-19 |
Deep trench isolation with surface contact to substrate Grant 4,980,747 - Hutter , et al. December 25, 1 | 1990-12-25 |
Trench bipolar transistor Grant 4,929,996 - Hutter May 29, 1 | 1990-05-29 |
Method of making vertical PNP transistor in merged bipolar/CMOS technology Grant 4,855,244 - Hutter , et al. August 8, 1 | 1989-08-08 |
Merged bipolar/CMOS technology using electrically active trench Grant 4,819,052 - Hutter April 4, 1 | 1989-04-04 |
High voltage capacitor for integrated circuits Grant 4,805,071 - Hutter , et al. February 14, 1 | 1989-02-14 |