Huster; Carl Robert
Patent Applications and Registrations
Patent applications and USPTO patent grants for Huster; Carl Robert.The latest application filed is for "selective epitaxy to reduce gate/gate dielectric interface roughness".
- Huster; Carl Robert - San Jose CA
- Huster; Carl Robert - Sunnyvale CA
| Patent | Date |
|---|---|
| Selective epitaxy to reduce gate/gate dielectric interface roughness Grant 6,548,335 - Huster , et al. April 15, 2 | 2003-04-15 |
| Optimized single side pocket implant location for a field effect transistor Grant 6,396,103 - Riccobene , et al. May 28, 2 | 2002-05-28 |
| Solid-source doping for source/drain to eliminate implant damage Grant 6,329,273 - Thurgate , et al. December 11, 2 | 2001-12-11 |
| Nitride plug to reduce gate edge lifting Grant 6,255,165 - Thurgate , et al. July 3, 2 | 2001-07-03 |
| Method for manufacturing asymmetric channel transistor Grant 6,242,329 - Huster , et al. June 5, 2 | 2001-06-05 |
| Use of etch to blunt gate corners Grant 6,238,978 - Huster May 29, 2 | 2001-05-29 |
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